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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jmp_ind.v] - Blame information for rev 5

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BYTE_JMP_IND1:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_JMP_IND2;
        end
        else if (dhit) begin
                pc[7:0] <= rdat8;
                radr <= radr34p1[33:2];
                radr2LSB <= radr34p1[1:0];
                state <= BYTE_JMP_IND3;
        end
        else
                dmiss <= `TRUE;
BYTE_JMP_IND2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'd0;
                radr <= radr34p1[33:2];
                radr2LSB <= radr34p1[1:0];
                pc[7:0] <= dati;
                state <= BYTE_JMP_IND3;
        end
BYTE_JMP_IND3:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_JMP_IND4;
        end
        else if (dhit) begin
                pc[15:8] <= rdat8;
                state <= IFETCH;
        end
        else
                dmiss <= `TRUE;
BYTE_JMP_IND4:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'd0;
                pc[15:8] <= dati;
                state <= IFETCH;
        end

Line No.	Rev	Author	Line
1	5	robfinch	`BYTE_JMP_IND1:`
2			`if (unCachedData) begin`
3			`cyc_o <= 1'b1;`
4			`stb_o <= 1'b1;`
5			`sel_o <= 4'hF;`
6			`adr_o <= {radr,2'b00};`
7			`state <= BYTE_JMP_IND2;`
8			`end`
9			`else if (dhit) begin`
10			`pc[7:0] <= rdat8;`
11			`radr <= radr34p1[33:2];`
12			`radr2LSB <= radr34p1[1:0];`
13			`state <= BYTE_JMP_IND3;`
14			`end`
15			`else`
16			dmiss <= `TRUE;
17			`BYTE_JMP_IND2:`
18			`if (ack_i) begin`
19			`cyc_o <= 1'b0;`
20			`stb_o <= 1'b0;`
21			`sel_o <= 4'h0;`
22			`adr_o <= 34'd0;`
23			`radr <= radr34p1[33:2];`
24			`radr2LSB <= radr34p1[1:0];`
25			`pc[7:0] <= dati;`
26			`state <= BYTE_JMP_IND3;`
27			`end`
28			`BYTE_JMP_IND3:`
29			`if (unCachedData) begin`
30			`cyc_o <= 1'b1;`
31			`stb_o <= 1'b1;`
32			`sel_o <= 4'hF;`
33			`adr_o <= {radr,2'b00};`
34			`state <= BYTE_JMP_IND4;`
35			`end`
36			`else if (dhit) begin`
37			`pc[15:8] <= rdat8;`
38			`state <= IFETCH;`
39			`end`
40			`else`
41			dmiss <= `TRUE;
42			`BYTE_JMP_IND4:`
43			`if (ack_i) begin`
44			`cyc_o <= 1'b0;`
45			`stb_o <= 1'b0;`
46			`sel_o <= 4'h0;`
47			`adr_o <= 34'd0;`
48			`pc[15:8] <= dati;`
49			`state <= IFETCH;`
50			`end`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jmp_ind.v] - Blame information for rev 5