OpenCores
URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jsl.v] - Blame information for rev 10

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 robfinch 
// ============================================================================
2 
//        __
3 
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
4 
//    \  __ /    All rights reserved.
5 
//     \/_//     robfinch<remove>@opencores.org
6 
//       ||
7 
//
8 
// This source file is free software: you can redistribute it and/or modify
9 
// it under the terms of the GNU Lesser General Public License as published
10 
// by the Free Software Foundation, either version 3 of the License, or
11 
// (at your option) any later version.
12 
//
13 
// This source file is distributed in the hope that it will be useful,
14 
// but WITHOUT ANY WARRANTY; without even the implied warranty of
15 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 
// GNU General Public License for more details.
17 
//
18 
// You should have received a copy of the GNU General Public License
19 
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
20 
//
21 
// ============================================================================
22 
//
23 5 robfinch 
BYTE_JSL1:
24 
        if (ack_i) begin
25 10 robfinch 
                state <= BYTE_JSL2;
26 
                retstate <= BYTE_JSL2;
27 5 robfinch 
                cyc_o <= 1'b0;
28 
                stb_o <= 1'b0;
29 
                we_o <= 1'b0;
30 
                sel_o <= 4'h0;
31 
                if (dhit) begin
32 
                        wrsel <= sel_o;
33 
                        wr <= 1'b1;
34 
                end
35 10 robfinch 
                else if (write_allocate) begin
36 
                        state <= WAIT_DHIT;
37 
                        dmiss <= `TRUE;
38 
                end
39 5 robfinch 
        end
40 
BYTE_JSL2:
41 
        begin
42 
                radr <= {24'h1,sp[7:2]};
43 
                wadr <= {24'h1,sp[7:2]};
44 
                radr2LSB <= sp[1:0];
45 
                wadr2LSB <= sp[1:0];
46 
                wdat <= {4{pcp4[23:16]}};
47 
                cyc_o <= 1'b1;
48 
                stb_o <= 1'b1;
49 
                we_o <= 1'b1;
50 
                case(sp[1:0])
51 
                2'd0:   sel_o <= 4'b0001;
52 
                2'd1:   sel_o <= 4'b0010;
53 
                2'd2:   sel_o <= 4'b0100;
54 
                2'd3:   sel_o <= 4'b1000;
55 
                endcase
56 
                adr_o <= {24'h1,sp[7:2],2'b00};
57 
                dat_o <= {4{pcp4[23:16]}};
58 
                sp <= sp_dec;
59 
                state <= BYTE_JSL3;
60 
        end
61 
BYTE_JSL3:
62 
        if (ack_i) begin
63 10 robfinch 
                state <= BYTE_JSL4;
64 
                retstate <= BYTE_JSL4;
65 5 robfinch 
                cyc_o <= 1'b0;
66 
                stb_o <= 1'b0;
67 
                we_o <= 1'b0;
68 
                sel_o <= 4'h0;
69 
                if (dhit) begin
70 
                        wrsel <= sel_o;
71 
                        wr <= 1'b1;
72 
                end
73 10 robfinch 
                else if (write_allocate) begin
74 
                        state <= WAIT_DHIT;
75 
                        dmiss <= `TRUE;
76 
                end
77 5 robfinch 
        end
78 
BYTE_JSL4:
79 
        begin
80 
                radr <= {24'h1,sp[7:2]};
81 
                wadr <= {24'h1,sp[7:2]};
82 
                radr2LSB <= sp[1:0];
83 
                wadr2LSB <= sp[1:0];
84 
                wdat <= {4{pcp4[15:8]}};
85 
                cyc_o <= 1'b1;
86 
                stb_o <= 1'b1;
87 
                we_o <= 1'b1;
88 
                case(sp[1:0])
89 
                2'd0:   sel_o <= 4'b0001;
90 
                2'd1:   sel_o <= 4'b0010;
91 
                2'd2:   sel_o <= 4'b0100;
92 
                2'd3:   sel_o <= 4'b1000;
93 
                endcase
94 
                adr_o <= {24'h1,sp[7:2],2'b00};
95 
                dat_o <= {4{pcp4[15:8]}};
96 
                sp <= sp_dec;
97 
                state <= BYTE_JSL5;
98 
        end
99 
BYTE_JSL5:
100 
        if (ack_i) begin
101 10 robfinch 
                state <= BYTE_JSL6;
102 
                retstate <= BYTE_JSL6;
103 5 robfinch 
                cyc_o <= 1'b0;
104 
                stb_o <= 1'b0;
105 
                we_o <= 1'b0;
106 
                sel_o <= 4'h0;
107 
                if (dhit) begin
108 
                        wrsel <= sel_o;
109 
                        wr <= 1'b1;
110 
                end
111 10 robfinch 
                else if (write_allocate) begin
112 
                        state <= WAIT_DHIT;
113 
                        dmiss <= `TRUE;
114 
                end
115 5 robfinch 
        end
116 
BYTE_JSL6:
117 
        begin
118 
                radr <= {24'h1,sp[7:2]};
119 
                wadr <= {24'h1,sp[7:2]};
120 
                radr2LSB <= sp[1:0];
121 
                wadr2LSB <= sp[1:0];
122 
                wdat <= {4{pcp4[7:0]}};
123 
                cyc_o <= 1'b1;
124 
                stb_o <= 1'b1;
125 
                we_o <= 1'b1;
126 
                case(sp[1:0])
127 
                2'd0:   sel_o <= 4'b0001;
128 
                2'd1:   sel_o <= 4'b0010;
129 
                2'd2:   sel_o <= 4'b0100;
130 
                2'd3:   sel_o <= 4'b1000;
131 
                endcase
132 
                adr_o <= {24'h1,sp[7:2],2'b00};
133 
                dat_o <= {4{pcp4[7:0]}};
134 
                sp <= sp_dec;
135 
                state <= BYTE_JSL7;
136 
        end
137 
BYTE_JSL7:
138 
        if (ack_i) begin
139 10 robfinch 
                state <= IFETCH;
140 
                retstate <= IFETCH;
141 5 robfinch 
                cyc_o <= 1'b0;
142 
                stb_o <= 1'b0;
143 
                we_o <= 1'b0;
144 
                sel_o <= 4'h0;
145 
                if (dhit) begin
146 
                        wrsel <= sel_o;
147 
                        wr <= 1'b1;
148 
                end
149 10 robfinch 
                else if (write_allocate) begin
150 
                        state <= WAIT_DHIT;
151 
                        dmiss <= `TRUE;
152 
                end
153 5 robfinch 
                pc <= ir[39:8];
154 
        end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.