OpenCores
URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jsl.v] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 robfinch 
BYTE_JSL1:
2 
        if (ack_i) begin
3 
                cyc_o <= 1'b0;
4 
                stb_o <= 1'b0;
5 
                we_o <= 1'b0;
6 
                sel_o <= 4'h0;
7 
                if (dhit) begin
8 
                        wrsel <= sel_o;
9 
                        wr <= 1'b1;
10 
                end
11 
                state <= BYTE_JSL2;
12 
        end
13 
BYTE_JSL2:
14 
        begin
15 
                radr <= {24'h1,sp[7:2]};
16 
                wadr <= {24'h1,sp[7:2]};
17 
                radr2LSB <= sp[1:0];
18 
                wadr2LSB <= sp[1:0];
19 
                wdat <= {4{pcp4[23:16]}};
20 
                cyc_o <= 1'b1;
21 
                stb_o <= 1'b1;
22 
                we_o <= 1'b1;
23 
                case(sp[1:0])
24 
                2'd0:   sel_o <= 4'b0001;
25 
                2'd1:   sel_o <= 4'b0010;
26 
                2'd2:   sel_o <= 4'b0100;
27 
                2'd3:   sel_o <= 4'b1000;
28 
                endcase
29 
                adr_o <= {24'h1,sp[7:2],2'b00};
30 
                dat_o <= {4{pcp4[23:16]}};
31 
                sp <= sp_dec;
32 
                state <= BYTE_JSL3;
33 
        end
34 
BYTE_JSL3:
35 
        if (ack_i) begin
36 
                cyc_o <= 1'b0;
37 
                stb_o <= 1'b0;
38 
                we_o <= 1'b0;
39 
                sel_o <= 4'h0;
40 
                if (dhit) begin
41 
                        wrsel <= sel_o;
42 
                        wr <= 1'b1;
43 
                end
44 
                state <= BYTE_JSL4;
45 
        end
46 
BYTE_JSL4:
47 
        begin
48 
                radr <= {24'h1,sp[7:2]};
49 
                wadr <= {24'h1,sp[7:2]};
50 
                radr2LSB <= sp[1:0];
51 
                wadr2LSB <= sp[1:0];
52 
                wdat <= {4{pcp4[15:8]}};
53 
                cyc_o <= 1'b1;
54 
                stb_o <= 1'b1;
55 
                we_o <= 1'b1;
56 
                case(sp[1:0])
57 
                2'd0:   sel_o <= 4'b0001;
58 
                2'd1:   sel_o <= 4'b0010;
59 
                2'd2:   sel_o <= 4'b0100;
60 
                2'd3:   sel_o <= 4'b1000;
61 
                endcase
62 
                adr_o <= {24'h1,sp[7:2],2'b00};
63 
                dat_o <= {4{pcp4[15:8]}};
64 
                sp <= sp_dec;
65 
                state <= BYTE_JSL5;
66 
        end
67 
BYTE_JSL5:
68 
        if (ack_i) begin
69 
                cyc_o <= 1'b0;
70 
                stb_o <= 1'b0;
71 
                we_o <= 1'b0;
72 
                sel_o <= 4'h0;
73 
                if (dhit) begin
74 
                        wrsel <= sel_o;
75 
                        wr <= 1'b1;
76 
                end
77 
                state <= BYTE_JSL6;
78 
        end
79 
BYTE_JSL6:
80 
        begin
81 
                radr <= {24'h1,sp[7:2]};
82 
                wadr <= {24'h1,sp[7:2]};
83 
                radr2LSB <= sp[1:0];
84 
                wadr2LSB <= sp[1:0];
85 
                wdat <= {4{pcp4[7:0]}};
86 
                cyc_o <= 1'b1;
87 
                stb_o <= 1'b1;
88 
                we_o <= 1'b1;
89 
                case(sp[1:0])
90 
                2'd0:   sel_o <= 4'b0001;
91 
                2'd1:   sel_o <= 4'b0010;
92 
                2'd2:   sel_o <= 4'b0100;
93 
                2'd3:   sel_o <= 4'b1000;
94 
                endcase
95 
                adr_o <= {24'h1,sp[7:2],2'b00};
96 
                dat_o <= {4{pcp4[7:0]}};
97 
                sp <= sp_dec;
98 
                state <= BYTE_JSL7;
99 
        end
100 
BYTE_JSL7:
101 
        if (ack_i) begin
102 
                cyc_o <= 1'b0;
103 
                stb_o <= 1'b0;
104 
                we_o <= 1'b0;
105 
                sel_o <= 4'h0;
106 
                if (dhit) begin
107 
                        wrsel <= sel_o;
108 
                        wr <= 1'b1;
109 
                end
110 
                pc <= ir[39:8];
111 
                state <= IFETCH;
112 
        end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.