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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jsr.v] - Blame information for rev 21

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
BYTE_JSR1:
        if (ack_i) begin
                state <= BYTE_JSR2;
                retstate <= BYTE_JSR2;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        state <= WAIT_DHIT;
                        dmiss <= `TRUE;
                end
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_JSR2:
        begin
                radr <= {spage[31:8],sp[7:2]};
                wadr <= {spage[31:8],sp[7:2]};
                radr2LSB <= sp[1:0];
                wadr2LSB <= sp[1:0];
                wdat <= {4{pcp2[7:0]}};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                case(sp[1:0])
                2'd0:   sel_o <= 4'b0001;
                2'd1:   sel_o <= 4'b0010;
                2'd2:   sel_o <= 4'b0100;
                2'd3:   sel_o <= 4'b1000;
                endcase
                adr_o <= {spage[31:8],sp[7:2],2'b00};
                dat_o <= {4{pcp2[7:0]}};
                sp <= sp_dec;
                state <= BYTE_JSR3;
        end
BYTE_JSR3:
        if (ack_i) begin
                state <= IFETCH;
                retstate <= IFETCH;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                pc[15:0] <= ir[23:8];
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        state <= WAIT_DHIT;
                        dmiss <= `TRUE;
                end
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
 
BYTE_JSR_INDX1:
        if (ack_i) begin
                state <= BYTE_JSR_INDX2;
                retstate <= BYTE_JSR_INDX2;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        state <= WAIT_DHIT;
                        dmiss <= `TRUE;
                end
        end
BYTE_JSR_INDX2:
        begin
                radr <= {spage[31:8],sp[7:2]};
                wadr <= {spage[31:8],sp[7:2]};
                radr2LSB <= sp[1:0];
                wadr2LSB <= sp[1:0];
                wdat <= {4{pcp2[7:0]}};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                case(sp[1:0])
                2'd0:   sel_o <= 4'b0001;
                2'd1:   sel_o <= 4'b0010;
                2'd2:   sel_o <= 4'b0100;
                2'd3:   sel_o <= 4'b1000;
                endcase
                adr_o <= {spage[31:8],sp[7:2],2'b00};
                dat_o <= {4{pcp2[7:0]}};
                sp <= sp_dec;
                state <= BYTE_JSR_INDX3;
        end
BYTE_JSR_INDX3:
        if (ack_i) begin
                load_what <= `PC_70;
                state <= LOAD_MAC1;
                retstate <= LOAD_MAC1;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'd0;
                dat_o <= 32'd0;
                radr <= absx_address[15:2];
                radr2LSB <= absx_address[1:0];
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        state <= WAIT_DHIT;
                        dmiss <= `TRUE;
                end
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`BYTE_JSR1:`
24			`if (ack_i) begin`
25	10	robfinch	`state <= BYTE_JSR2;`
26			`retstate <= BYTE_JSR2;`
27	5	robfinch	`cyc_o <= 1'b0;`
28			`stb_o <= 1'b0;`
29			`we_o <= 1'b0;`
30			`sel_o <= 4'h0;`
31			`if (dhit) begin`
32			`wrsel <= sel_o;`
33			`wr <= 1'b1;`
34			`end`
35	10	robfinch	`else if (write_allocate) begin`
36			`state <= WAIT_DHIT;`
37			dmiss <= `TRUE;
38			`end`
39	5	robfinch	`end`
40	21	robfinch	`else if (err_i) begin`
41			`lock_o <= 1'b0;`
42			`cyc_o <= 1'b0;`
43			`stb_o <= 1'b0;`
44			`we_o <= 1'b0;`
45			`sel_o <= 4'h0;`
46			`adr_o <= 34'h0;`
47			`dat_o <= 32'h0;`
48			`state <= BUS_ERROR;`
49			`end`
50	5	robfinch	`BYTE_JSR2:`
51			`begin`
52	13	robfinch	`radr <= {spage[31:8],sp[7:2]};`
53			`wadr <= {spage[31:8],sp[7:2]};`
54	5	robfinch	`radr2LSB <= sp[1:0];`
55			`wadr2LSB <= sp[1:0];`
56			`wdat <= {4{pcp2[7:0]}};`
57			`cyc_o <= 1'b1;`
58			`stb_o <= 1'b1;`
59			`we_o <= 1'b1;`
60			`case(sp[1:0])`
61			`2'd0: sel_o <= 4'b0001;`
62			`2'd1: sel_o <= 4'b0010;`
63			`2'd2: sel_o <= 4'b0100;`
64			`2'd3: sel_o <= 4'b1000;`
65			`endcase`
66	13	robfinch	`adr_o <= {spage[31:8],sp[7:2],2'b00};`
67	5	robfinch	`dat_o <= {4{pcp2[7:0]}};`
68			`sp <= sp_dec;`
69			`state <= BYTE_JSR3;`
70			`end`
71			`BYTE_JSR3:`
72			`if (ack_i) begin`
73	10	robfinch	`state <= IFETCH;`
74			`retstate <= IFETCH;`
75	5	robfinch	`cyc_o <= 1'b0;`
76			`stb_o <= 1'b0;`
77			`we_o <= 1'b0;`
78			`sel_o <= 4'h0;`
79			`pc[15:0] <= ir[23:8];`
80			`if (dhit) begin`
81			`wrsel <= sel_o;`
82			`wr <= 1'b1;`
83			`end`
84	10	robfinch	`else if (write_allocate) begin`
85			`state <= WAIT_DHIT;`
86			dmiss <= `TRUE;
87			`end`
88	5	robfinch	`end`
89	21	robfinch	`else if (err_i) begin`
90			`lock_o <= 1'b0;`
91			`cyc_o <= 1'b0;`
92			`stb_o <= 1'b0;`
93			`we_o <= 1'b0;`
94			`sel_o <= 4'h0;`
95			`adr_o <= 34'h0;`
96			`dat_o <= 32'h0;`
97			`state <= BUS_ERROR;`
98			`end`
99	20	robfinch
100			`BYTE_JSR_INDX1:`
101			`if (ack_i) begin`
102			`state <= BYTE_JSR_INDX2;`
103			`retstate <= BYTE_JSR_INDX2;`
104			`cyc_o <= 1'b0;`
105			`stb_o <= 1'b0;`
106			`we_o <= 1'b0;`
107			`sel_o <= 4'h0;`
108			`if (dhit) begin`
109			`wrsel <= sel_o;`
110			`wr <= 1'b1;`
111			`end`
112			`else if (write_allocate) begin`
113			`state <= WAIT_DHIT;`
114			dmiss <= `TRUE;
115			`end`
116			`end`
117			`BYTE_JSR_INDX2:`
118			`begin`
119			`radr <= {spage[31:8],sp[7:2]};`
120			`wadr <= {spage[31:8],sp[7:2]};`
121			`radr2LSB <= sp[1:0];`
122			`wadr2LSB <= sp[1:0];`
123			`wdat <= {4{pcp2[7:0]}};`
124			`cyc_o <= 1'b1;`
125			`stb_o <= 1'b1;`
126			`we_o <= 1'b1;`
127			`case(sp[1:0])`
128			`2'd0: sel_o <= 4'b0001;`
129			`2'd1: sel_o <= 4'b0010;`
130			`2'd2: sel_o <= 4'b0100;`
131			`2'd3: sel_o <= 4'b1000;`
132			`endcase`
133			`adr_o <= {spage[31:8],sp[7:2],2'b00};`
134			`dat_o <= {4{pcp2[7:0]}};`
135			`sp <= sp_dec;`
136			`state <= BYTE_JSR_INDX3;`
137			`end`
138			`BYTE_JSR_INDX3:`
139			`if (ack_i) begin`
140	21	robfinch	load_what <= `PC_70;
141			`state <= LOAD_MAC1;`
142			`retstate <= LOAD_MAC1;`
143	20	robfinch	`cyc_o <= 1'b0;`
144			`stb_o <= 1'b0;`
145			`we_o <= 1'b0;`
146			`sel_o <= 4'h0;`
147			`adr_o <= 34'd0;`
148			`dat_o <= 32'd0;`
149			`radr <= absx_address[15:2];`
150			`radr2LSB <= absx_address[1:0];`
151			`if (dhit) begin`
152			`wrsel <= sel_o;`
153			`wr <= 1'b1;`
154			`end`
155			`else if (write_allocate) begin`
156			`state <= WAIT_DHIT;`
157			dmiss <= `TRUE;
158			`end`
159			`end`
160	21	robfinch	`else if (err_i) begin`
161			`lock_o <= 1'b0;`
162			`cyc_o <= 1'b0;`
163			`stb_o <= 1'b0;`
164			`we_o <= 1'b0;`
165			`sel_o <= 4'h0;`
166			`adr_o <= 34'h0;`
167			`dat_o <= 32'h0;`
168			`state <= BUS_ERROR;`
169			`end`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jsr.v] - Blame information for rev 21