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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jsr.v] - Blame information for rev 28

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
BYTE_JSR1:
        if (ack_i) begin
                state <= BYTE_JSR2;
                retstate <= BYTE_JSR2;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        state <= WAIT_DHIT;
                        dmiss <= `TRUE;
                end
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_JSR2:
        begin
                radr <= {spage[31:8],sp[7:2]};
                wadr <= {spage[31:8],sp[7:2]};
                radr2LSB <= sp[1:0];
                wadr2LSB <= sp[1:0];
                wdat <= {4{pcp2[7:0]}};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                case(sp[1:0])
                2'd0:   sel_o <= 4'b0001;
                2'd1:   sel_o <= 4'b0010;
                2'd2:   sel_o <= 4'b0100;
                2'd3:   sel_o <= 4'b1000;
                endcase
                adr_o <= {spage[31:8],sp[7:2],2'b00};
                dat_o <= {4{pcp2[7:0]}};
                sp <= sp_dec;
                state <= BYTE_JSR3;
        end
BYTE_JSR3:
        if (ack_i) begin
                state <= IFETCH;
                retstate <= IFETCH;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                pc[15:0] <= ir[23:8];
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        state <= WAIT_DHIT;
                        dmiss <= `TRUE;
                end
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
 
BYTE_JSR_INDX1:
        if (ack_i) begin
                state <= BYTE_JSR_INDX2;
                retstate <= BYTE_JSR_INDX2;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        state <= WAIT_DHIT;
                        dmiss <= `TRUE;
                end
        end
BYTE_JSR_INDX2:
        begin
                radr <= {spage[31:8],sp[7:2]};
                wadr <= {spage[31:8],sp[7:2]};
                radr2LSB <= sp[1:0];
                wadr2LSB <= sp[1:0];
                wdat <= {4{pcp2[7:0]}};
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                case(sp[1:0])
                2'd0:   sel_o <= 4'b0001;
                2'd1:   sel_o <= 4'b0010;
                2'd2:   sel_o <= 4'b0100;
                2'd3:   sel_o <= 4'b1000;
                endcase
                adr_o <= {spage[31:8],sp[7:2],2'b00};
                dat_o <= {4{pcp2[7:0]}};
                sp <= sp_dec;
                state <= BYTE_JSR_INDX3;
        end
BYTE_JSR_INDX3:
        if (ack_i) begin
                load_what <= `PC_70;
                state <= LOAD_MAC1;
                retstate <= LOAD_MAC1;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'd0;
                dat_o <= 32'd0;
                radr <= absx_address[15:2];
                radr2LSB <= absx_address[1:0];
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        state <= WAIT_DHIT;
                        dmiss <= `TRUE;
                end
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`BYTE_JSR1:`
24			`if (ack_i) begin`
25	10	robfinch	`state <= BYTE_JSR2;`
26			`retstate <= BYTE_JSR2;`
27	5	robfinch	`cyc_o <= 1'b0;`
28			`stb_o <= 1'b0;`
29			`we_o <= 1'b0;`
30			`sel_o <= 4'h0;`
31			`if (dhit) begin`
32			`wrsel <= sel_o;`
33			`wr <= 1'b1;`
34			`end`
35	10	robfinch	`else if (write_allocate) begin`
36			`state <= WAIT_DHIT;`
37			dmiss <= `TRUE;
38			`end`
39	5	robfinch	`end`
40	21	robfinch	`else if (err_i) begin`
41			`lock_o <= 1'b0;`
42			`cyc_o <= 1'b0;`
43			`stb_o <= 1'b0;`
44			`we_o <= 1'b0;`
45			`sel_o <= 4'h0;`
46			`dat_o <= 32'h0;`
47			`state <= BUS_ERROR;`
48			`end`
49	5	robfinch	`BYTE_JSR2:`
50			`begin`
51	13	robfinch	`radr <= {spage[31:8],sp[7:2]};`
52			`wadr <= {spage[31:8],sp[7:2]};`
53	5	robfinch	`radr2LSB <= sp[1:0];`
54			`wadr2LSB <= sp[1:0];`
55			`wdat <= {4{pcp2[7:0]}};`
56			`cyc_o <= 1'b1;`
57			`stb_o <= 1'b1;`
58			`we_o <= 1'b1;`
59			`case(sp[1:0])`
60			`2'd0: sel_o <= 4'b0001;`
61			`2'd1: sel_o <= 4'b0010;`
62			`2'd2: sel_o <= 4'b0100;`
63			`2'd3: sel_o <= 4'b1000;`
64			`endcase`
65	13	robfinch	`adr_o <= {spage[31:8],sp[7:2],2'b00};`
66	5	robfinch	`dat_o <= {4{pcp2[7:0]}};`
67			`sp <= sp_dec;`
68			`state <= BYTE_JSR3;`
69			`end`
70			`BYTE_JSR3:`
71			`if (ack_i) begin`
72	10	robfinch	`state <= IFETCH;`
73			`retstate <= IFETCH;`
74	5	robfinch	`cyc_o <= 1'b0;`
75			`stb_o <= 1'b0;`
76			`we_o <= 1'b0;`
77			`sel_o <= 4'h0;`
78			`pc[15:0] <= ir[23:8];`
79			`if (dhit) begin`
80			`wrsel <= sel_o;`
81			`wr <= 1'b1;`
82			`end`
83	10	robfinch	`else if (write_allocate) begin`
84			`state <= WAIT_DHIT;`
85			dmiss <= `TRUE;
86			`end`
87	5	robfinch	`end`
88	21	robfinch	`else if (err_i) begin`
89			`lock_o <= 1'b0;`
90			`cyc_o <= 1'b0;`
91			`stb_o <= 1'b0;`
92			`we_o <= 1'b0;`
93			`sel_o <= 4'h0;`
94			`dat_o <= 32'h0;`
95			`state <= BUS_ERROR;`
96			`end`
97	20	robfinch
98			`BYTE_JSR_INDX1:`
99			`if (ack_i) begin`
100			`state <= BYTE_JSR_INDX2;`
101			`retstate <= BYTE_JSR_INDX2;`
102			`cyc_o <= 1'b0;`
103			`stb_o <= 1'b0;`
104			`we_o <= 1'b0;`
105			`sel_o <= 4'h0;`
106			`if (dhit) begin`
107			`wrsel <= sel_o;`
108			`wr <= 1'b1;`
109			`end`
110			`else if (write_allocate) begin`
111			`state <= WAIT_DHIT;`
112			dmiss <= `TRUE;
113			`end`
114			`end`
115			`BYTE_JSR_INDX2:`
116			`begin`
117			`radr <= {spage[31:8],sp[7:2]};`
118			`wadr <= {spage[31:8],sp[7:2]};`
119			`radr2LSB <= sp[1:0];`
120			`wadr2LSB <= sp[1:0];`
121			`wdat <= {4{pcp2[7:0]}};`
122			`cyc_o <= 1'b1;`
123			`stb_o <= 1'b1;`
124			`we_o <= 1'b1;`
125			`case(sp[1:0])`
126			`2'd0: sel_o <= 4'b0001;`
127			`2'd1: sel_o <= 4'b0010;`
128			`2'd2: sel_o <= 4'b0100;`
129			`2'd3: sel_o <= 4'b1000;`
130			`endcase`
131			`adr_o <= {spage[31:8],sp[7:2],2'b00};`
132			`dat_o <= {4{pcp2[7:0]}};`
133			`sp <= sp_dec;`
134			`state <= BYTE_JSR_INDX3;`
135			`end`
136			`BYTE_JSR_INDX3:`
137			`if (ack_i) begin`
138	21	robfinch	load_what <= `PC_70;
139			`state <= LOAD_MAC1;`
140			`retstate <= LOAD_MAC1;`
141	20	robfinch	`cyc_o <= 1'b0;`
142			`stb_o <= 1'b0;`
143			`we_o <= 1'b0;`
144			`sel_o <= 4'h0;`
145			`adr_o <= 34'd0;`
146			`dat_o <= 32'd0;`
147			`radr <= absx_address[15:2];`
148			`radr2LSB <= absx_address[1:0];`
149			`if (dhit) begin`
150			`wrsel <= sel_o;`
151			`wr <= 1'b1;`
152			`end`
153			`else if (write_allocate) begin`
154			`state <= WAIT_DHIT;`
155			dmiss <= `TRUE;
156			`end`
157			`end`
158	21	robfinch	`else if (err_i) begin`
159			`lock_o <= 1'b0;`
160			`cyc_o <= 1'b0;`
161			`stb_o <= 1'b0;`
162			`we_o <= 1'b0;`
163			`sel_o <= 4'h0;`
164			`dat_o <= 32'h0;`
165			`state <= BUS_ERROR;`
166			`end`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jsr.v] - Blame information for rev 28