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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_plp.v] - Blame information for rev 5

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Line No. Rev Author Line
1 5 robfinch 
BYTE_PLP1:
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        if (unCachedData) begin
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                sel_o <= 4'hF;
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                adr_o <= {radr,2'b00};
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                state <= BYTE_PLP2;
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        end
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        else if (dhit) begin
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                cf <= rdat8[0];
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                zf <= rdat8[1];
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                im <= rdat8[2];
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                df <= rdat8[3];
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                bf <= rdat8[4];
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                vf <= rdat8[6];
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                nf <= rdat8[7];
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                state <= IFETCH;
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        end
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        else
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                dmiss <= `TRUE;
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BYTE_PLP2:
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        if (ack_i) begin
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                sel_o <= 4'h0;
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                cf <= dati[0];
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                zf <= dati[1];
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                im <= dati[2];
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                df <= dati[3];
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                bf <= dati[4];
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                vf <= dati[6];
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                nf <= dati[7];
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                state <= IFETCH;
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        end

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