URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rti.v] - Blame information for rev 13

Go to most recent revision | Details | Compare with Previous | View Log


// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
// RTI processing states for eight bit mode
//
BYTE_RTI9:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTI10;
        end
        else if (dhit) begin
                cf <= rdat8[0];
                zf <= rdat8[1];
                im <= rdat8[2];
                df <= rdat8[3];
                bf <= rdat8[4];
                vf <= rdat8[6];
                nf <= rdat8[7];
                sp <= sp_inc;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                state <= BYTE_RTI1;
        end
        else
                dmiss <= `TRUE;
BYTE_RTI10:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                cf <= dati[0];
                zf <= dati[1];
                im <= dati[2];
                df <= dati[3];
                bf <= dati[4];
                vf <= dati[6];
                nf <= dati[7];
                sp <= sp_inc;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                state <= BYTE_RTI1;
        end
BYTE_RTI1:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= RTI2;
        end
        else if (dhit) begin
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[7:0] <= rdat8;
                state <= BYTE_RTI3;
        end
        else
                dmiss <= `TRUE;
BYTE_RTI2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[7:0] <= dati;
                state <= BYTE_RTI3;
        end
BYTE_RTI3:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTI4;
        end
        else if (dhit) begin
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[15:8] <= rdat8;
                state <= BYTE_RTI5;
        end
        else
                dmiss <= `TRUE;
BYTE_RTI4:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[15:8] <= dati;
                state <= BYTE_RTI5;
        end
BYTE_RTI5:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTI6;
        end
        else if (dhit) begin
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[23:16] <= rdat8;
                state <= BYTE_RTI7;
        end
        else
                dmiss <= `TRUE;
BYTE_RTI6:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[23:16] <= dati;
                state <= BYTE_RTI7;
        end
BYTE_RTI7:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTI8;
        end
        else if (dhit) begin
                pc[31:24] <= rdat8;
                state <= IFETCH;
        end
        else
                dmiss <= `TRUE;
BYTE_RTI8:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                pc[31:24] <= dati;
                state <= IFETCH;
        end

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`// RTI processing states for eight bit mode`
24			`//`
25			`BYTE_RTI9:`
26			`if (unCachedData) begin`
27			`cyc_o <= 1'b1;`
28			`stb_o <= 1'b1;`
29			`sel_o <= 4'hF;`
30			`adr_o <= {radr,2'b00};`
31			`state <= BYTE_RTI10;`
32			`end`
33			`else if (dhit) begin`
34			`cf <= rdat8[0];`
35			`zf <= rdat8[1];`
36			`im <= rdat8[2];`
37			`df <= rdat8[3];`
38			`bf <= rdat8[4];`
39			`vf <= rdat8[6];`
40			`nf <= rdat8[7];`
41			`sp <= sp_inc;`
42	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
43	5	robfinch	`radr2LSB <= sp_inc[1:0];`
44			`state <= BYTE_RTI1;`
45			`end`
46			`else`
47			dmiss <= `TRUE;
48			`BYTE_RTI10:`
49			`if (ack_i) begin`
50			`cyc_o <= 1'b0;`
51			`stb_o <= 1'b0;`
52			`sel_o <= 4'h0;`
53			`cf <= dati[0];`
54			`zf <= dati[1];`
55			`im <= dati[2];`
56			`df <= dati[3];`
57			`bf <= dati[4];`
58			`vf <= dati[6];`
59			`nf <= dati[7];`
60			`sp <= sp_inc;`
61	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
62	5	robfinch	`radr2LSB <= sp_inc[1:0];`
63			`state <= BYTE_RTI1;`
64			`end`
65			`BYTE_RTI1:`
66			`if (unCachedData) begin`
67			`cyc_o <= 1'b1;`
68			`stb_o <= 1'b1;`
69			`sel_o <= 4'hF;`
70			`adr_o <= {radr,2'b00};`
71			`state <= RTI2;`
72			`end`
73			`else if (dhit) begin`
74	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
75	5	robfinch	`radr2LSB <= sp_inc[1:0];`
76			`sp <= sp_inc;`
77			`pc[7:0] <= rdat8;`
78			`state <= BYTE_RTI3;`
79			`end`
80			`else`
81			dmiss <= `TRUE;
82			`BYTE_RTI2:`
83			`if (ack_i) begin`
84			`cyc_o <= 1'b0;`
85			`stb_o <= 1'b0;`
86			`sel_o <= 4'h0;`
87			`adr_o <= 34'h0;`
88	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
89	5	robfinch	`radr2LSB <= sp_inc[1:0];`
90			`sp <= sp_inc;`
91			`pc[7:0] <= dati;`
92			`state <= BYTE_RTI3;`
93			`end`
94			`BYTE_RTI3:`
95			`if (unCachedData) begin`
96			`cyc_o <= 1'b1;`
97			`stb_o <= 1'b1;`
98			`sel_o <= 4'hF;`
99			`adr_o <= {radr,2'b00};`
100			`state <= BYTE_RTI4;`
101			`end`
102			`else if (dhit) begin`
103	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
104	5	robfinch	`radr2LSB <= sp_inc[1:0];`
105			`sp <= sp_inc;`
106			`pc[15:8] <= rdat8;`
107			`state <= BYTE_RTI5;`
108			`end`
109			`else`
110			dmiss <= `TRUE;
111			`BYTE_RTI4:`
112			`if (ack_i) begin`
113			`cyc_o <= 1'b0;`
114			`stb_o <= 1'b0;`
115			`sel_o <= 4'h0;`
116			`adr_o <= 34'h0;`
117	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
118	5	robfinch	`radr2LSB <= sp_inc[1:0];`
119			`sp <= sp_inc;`
120			`pc[15:8] <= dati;`
121			`state <= BYTE_RTI5;`
122			`end`
123			`BYTE_RTI5:`
124			`if (unCachedData) begin`
125			`cyc_o <= 1'b1;`
126			`stb_o <= 1'b1;`
127			`sel_o <= 4'hF;`
128			`adr_o <= {radr,2'b00};`
129			`state <= BYTE_RTI6;`
130			`end`
131			`else if (dhit) begin`
132	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
133	5	robfinch	`radr2LSB <= sp_inc[1:0];`
134			`sp <= sp_inc;`
135			`pc[23:16] <= rdat8;`
136			`state <= BYTE_RTI7;`
137			`end`
138			`else`
139			dmiss <= `TRUE;
140			`BYTE_RTI6:`
141			`if (ack_i) begin`
142			`cyc_o <= 1'b0;`
143			`stb_o <= 1'b0;`
144			`sel_o <= 4'h0;`
145			`adr_o <= 34'h0;`
146	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
147	5	robfinch	`radr2LSB <= sp_inc[1:0];`
148			`sp <= sp_inc;`
149			`pc[23:16] <= dati;`
150			`state <= BYTE_RTI7;`
151			`end`
152			`BYTE_RTI7:`
153			`if (unCachedData) begin`
154			`cyc_o <= 1'b1;`
155			`stb_o <= 1'b1;`
156			`sel_o <= 4'hF;`
157			`adr_o <= {radr,2'b00};`
158			`state <= BYTE_RTI8;`
159			`end`
160			`else if (dhit) begin`
161			`pc[31:24] <= rdat8;`
162			`state <= IFETCH;`
163			`end`
164			`else`
165			dmiss <= `TRUE;
166			`BYTE_RTI8:`
167			`if (ack_i) begin`
168			`cyc_o <= 1'b0;`
169			`stb_o <= 1'b0;`
170			`sel_o <= 4'h0;`
171			`adr_o <= 34'h0;`
172			`pc[31:24] <= dati;`
173			`state <= IFETCH;`
174			`end`

Browse

Tools

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rti.v] - Blame information for rev 13