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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rti.v] - Blame information for rev 21

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
// RTI processing states for eight bit mode
//
BYTE_RTI9:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTI10;
        end
        else if (dhit) begin
                cf <= rdat8[0];
                zf <= rdat8[1];
                im <= rdat8[2];
                df <= rdat8[3];
                bf <= rdat8[4];
                vf <= rdat8[6];
                nf <= rdat8[7];
                sp <= sp_inc;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                state <= BYTE_RTI1;
        end
        else
                dmiss <= `TRUE;
BYTE_RTI10:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                cf <= dati[0];
                zf <= dati[1];
                im <= dati[2];
                df <= dati[3];
                bf <= dati[4];
                vf <= dati[6];
                nf <= dati[7];
                sp <= sp_inc;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                state <= BYTE_RTI1;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_RTI1:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= RTI2;
        end
        else if (dhit) begin
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[7:0] <= rdat8;
                state <= BYTE_RTI3;
        end
        else
                dmiss <= `TRUE;
BYTE_RTI2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[7:0] <= dati;
                state <= BYTE_RTI3;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_RTI3:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTI4;
        end
        else if (dhit) begin
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[15:8] <= rdat8;
                state <= BYTE_RTI5;
        end
        else
                dmiss <= `TRUE;
BYTE_RTI4:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[15:8] <= dati;
                state <= BYTE_RTI5;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_RTI5:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTI6;
        end
        else if (dhit) begin
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[23:16] <= rdat8;
                state <= BYTE_RTI7;
        end
        else
                dmiss <= `TRUE;
BYTE_RTI6:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[23:16] <= dati;
                state <= BYTE_RTI7;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_RTI7:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTI8;
        end
        else if (dhit) begin
                pc[31:24] <= rdat8;
                state <= IFETCH;
        end
        else
                dmiss <= `TRUE;
BYTE_RTI8:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                pc[31:24] <= dati;
                state <= IFETCH;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`// RTI processing states for eight bit mode`
24			`//`
25			`BYTE_RTI9:`
26			`if (unCachedData) begin`
27			`cyc_o <= 1'b1;`
28			`stb_o <= 1'b1;`
29			`sel_o <= 4'hF;`
30			`adr_o <= {radr,2'b00};`
31			`state <= BYTE_RTI10;`
32			`end`
33			`else if (dhit) begin`
34			`cf <= rdat8[0];`
35			`zf <= rdat8[1];`
36			`im <= rdat8[2];`
37			`df <= rdat8[3];`
38			`bf <= rdat8[4];`
39			`vf <= rdat8[6];`
40			`nf <= rdat8[7];`
41			`sp <= sp_inc;`
42	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
43	5	robfinch	`radr2LSB <= sp_inc[1:0];`
44			`state <= BYTE_RTI1;`
45			`end`
46			`else`
47			dmiss <= `TRUE;
48			`BYTE_RTI10:`
49			`if (ack_i) begin`
50			`cyc_o <= 1'b0;`
51			`stb_o <= 1'b0;`
52			`sel_o <= 4'h0;`
53			`cf <= dati[0];`
54			`zf <= dati[1];`
55			`im <= dati[2];`
56			`df <= dati[3];`
57			`bf <= dati[4];`
58			`vf <= dati[6];`
59			`nf <= dati[7];`
60			`sp <= sp_inc;`
61	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
62	5	robfinch	`radr2LSB <= sp_inc[1:0];`
63			`state <= BYTE_RTI1;`
64			`end`
65	21	robfinch	`else if (err_i) begin`
66			`lock_o <= 1'b0;`
67			`cyc_o <= 1'b0;`
68			`stb_o <= 1'b0;`
69			`we_o <= 1'b0;`
70			`sel_o <= 4'h0;`
71			`adr_o <= 34'h0;`
72			`dat_o <= 32'h0;`
73			`state <= BUS_ERROR;`
74			`end`
75	5	robfinch	`BYTE_RTI1:`
76			`if (unCachedData) begin`
77			`cyc_o <= 1'b1;`
78			`stb_o <= 1'b1;`
79			`sel_o <= 4'hF;`
80			`adr_o <= {radr,2'b00};`
81			`state <= RTI2;`
82			`end`
83			`else if (dhit) begin`
84	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
85	5	robfinch	`radr2LSB <= sp_inc[1:0];`
86			`sp <= sp_inc;`
87			`pc[7:0] <= rdat8;`
88			`state <= BYTE_RTI3;`
89			`end`
90			`else`
91			dmiss <= `TRUE;
92			`BYTE_RTI2:`
93			`if (ack_i) begin`
94			`cyc_o <= 1'b0;`
95			`stb_o <= 1'b0;`
96			`sel_o <= 4'h0;`
97			`adr_o <= 34'h0;`
98	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
99	5	robfinch	`radr2LSB <= sp_inc[1:0];`
100			`sp <= sp_inc;`
101			`pc[7:0] <= dati;`
102			`state <= BYTE_RTI3;`
103			`end`
104	21	robfinch	`else if (err_i) begin`
105			`lock_o <= 1'b0;`
106			`cyc_o <= 1'b0;`
107			`stb_o <= 1'b0;`
108			`we_o <= 1'b0;`
109			`sel_o <= 4'h0;`
110			`adr_o <= 34'h0;`
111			`dat_o <= 32'h0;`
112			`state <= BUS_ERROR;`
113			`end`
114	5	robfinch	`BYTE_RTI3:`
115			`if (unCachedData) begin`
116			`cyc_o <= 1'b1;`
117			`stb_o <= 1'b1;`
118			`sel_o <= 4'hF;`
119			`adr_o <= {radr,2'b00};`
120			`state <= BYTE_RTI4;`
121			`end`
122			`else if (dhit) begin`
123	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
124	5	robfinch	`radr2LSB <= sp_inc[1:0];`
125			`sp <= sp_inc;`
126			`pc[15:8] <= rdat8;`
127			`state <= BYTE_RTI5;`
128			`end`
129			`else`
130			dmiss <= `TRUE;
131			`BYTE_RTI4:`
132			`if (ack_i) begin`
133			`cyc_o <= 1'b0;`
134			`stb_o <= 1'b0;`
135			`sel_o <= 4'h0;`
136			`adr_o <= 34'h0;`
137	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
138	5	robfinch	`radr2LSB <= sp_inc[1:0];`
139			`sp <= sp_inc;`
140			`pc[15:8] <= dati;`
141			`state <= BYTE_RTI5;`
142			`end`
143	21	robfinch	`else if (err_i) begin`
144			`lock_o <= 1'b0;`
145			`cyc_o <= 1'b0;`
146			`stb_o <= 1'b0;`
147			`we_o <= 1'b0;`
148			`sel_o <= 4'h0;`
149			`adr_o <= 34'h0;`
150			`dat_o <= 32'h0;`
151			`state <= BUS_ERROR;`
152			`end`
153	5	robfinch	`BYTE_RTI5:`
154			`if (unCachedData) begin`
155			`cyc_o <= 1'b1;`
156			`stb_o <= 1'b1;`
157			`sel_o <= 4'hF;`
158			`adr_o <= {radr,2'b00};`
159			`state <= BYTE_RTI6;`
160			`end`
161			`else if (dhit) begin`
162	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
163	5	robfinch	`radr2LSB <= sp_inc[1:0];`
164			`sp <= sp_inc;`
165			`pc[23:16] <= rdat8;`
166			`state <= BYTE_RTI7;`
167			`end`
168			`else`
169			dmiss <= `TRUE;
170			`BYTE_RTI6:`
171			`if (ack_i) begin`
172			`cyc_o <= 1'b0;`
173			`stb_o <= 1'b0;`
174			`sel_o <= 4'h0;`
175			`adr_o <= 34'h0;`
176	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
177	5	robfinch	`radr2LSB <= sp_inc[1:0];`
178			`sp <= sp_inc;`
179			`pc[23:16] <= dati;`
180			`state <= BYTE_RTI7;`
181			`end`
182	21	robfinch	`else if (err_i) begin`
183			`lock_o <= 1'b0;`
184			`cyc_o <= 1'b0;`
185			`stb_o <= 1'b0;`
186			`we_o <= 1'b0;`
187			`sel_o <= 4'h0;`
188			`adr_o <= 34'h0;`
189			`dat_o <= 32'h0;`
190			`state <= BUS_ERROR;`
191			`end`
192	5	robfinch	`BYTE_RTI7:`
193			`if (unCachedData) begin`
194			`cyc_o <= 1'b1;`
195			`stb_o <= 1'b1;`
196			`sel_o <= 4'hF;`
197			`adr_o <= {radr,2'b00};`
198			`state <= BYTE_RTI8;`
199			`end`
200			`else if (dhit) begin`
201			`pc[31:24] <= rdat8;`
202			`state <= IFETCH;`
203			`end`
204			`else`
205			dmiss <= `TRUE;
206			`BYTE_RTI8:`
207			`if (ack_i) begin`
208			`cyc_o <= 1'b0;`
209			`stb_o <= 1'b0;`
210			`sel_o <= 4'h0;`
211			`adr_o <= 34'h0;`
212			`pc[31:24] <= dati;`
213			`state <= IFETCH;`
214			`end`
215	21	robfinch	`else if (err_i) begin`
216			`lock_o <= 1'b0;`
217			`cyc_o <= 1'b0;`
218			`stb_o <= 1'b0;`
219			`we_o <= 1'b0;`
220			`sel_o <= 4'h0;`
221			`adr_o <= 34'h0;`
222			`dat_o <= 32'h0;`
223			`state <= BUS_ERROR;`
224			`end`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rti.v] - Blame information for rev 21