URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rts.v] - Blame information for rev 21

Details | Compare with Previous | View Log


// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
// Eight bit mode RTS/RTL states
//
BYTE_RTS1:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTS2;
        end
        else if (dhit) begin
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[7:0] <= rdat8;
                state <= BYTE_RTS3;
        end
        else
                dmiss <= `TRUE;
BYTE_RTS2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[7:0] <= dati;
                state <= BYTE_RTS3;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_RTS3:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTS4;
        end
        else if (dhit) begin
                if (ir[7:0]==`RTL) begin
                        radr <= {spage[31:8],sp_inc[7:2]};
                        radr2LSB <= sp_inc[1:0];
                        sp <= sp_inc;
                end
                pc[15:8] <= rdat8;
                state <= BYTE_RTS5;
        end
        else
                dmiss <= `TRUE;
BYTE_RTS4:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                pc[15:8] <= dati;
                if (ir[7:0]==`RTL) begin
                        radr <= {spage[31:8],sp_inc[7:2]};
                        radr2LSB <= sp_inc[1:0];
                        sp <= sp_inc;
                end
                state <= BYTE_RTS5;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_RTS5:
        if (ir[7:0]!=`RTL) begin
                pc <= pc + 32'd1;
                state <= IFETCH;
        end
        else begin
                if (unCachedData) begin
                        cyc_o <= 1'b1;
                        stb_o <= 1'b1;
                        sel_o <= 4'hF;
                        adr_o <= {radr,2'b00};
                        state <= BYTE_RTS6;
                end
                else if (dhit) begin
                        radr <= {spage[31:8],sp_inc[7:2]};
                        radr2LSB <= sp_inc[1:0];
                        sp <= sp_inc;
                        pc[23:16] <= rdat8;
                        state <= BYTE_RTS7;
                end
                else
                        dmiss <= `TRUE;
        end
BYTE_RTS6:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                pc[23:16] <= dati;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                state <= BYTE_RTS7;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_RTS7:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTS8;
        end
        else if (dhit) begin
                pc[31:24] <= rdat8;
                state <= BYTE_RTS9;
        end
        else
                dmiss <= `TRUE;
BYTE_RTS8:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                pc[31:24] <= dati;
                state <= BYTE_RTS9;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_RTS9:
        begin
                pc <= pc + 32'd1;
                state <= IFETCH;
        end
 

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`// Eight bit mode RTS/RTL states`
24			`//`
25			`BYTE_RTS1:`
26			`if (unCachedData) begin`
27			`cyc_o <= 1'b1;`
28			`stb_o <= 1'b1;`
29			`sel_o <= 4'hF;`
30			`adr_o <= {radr,2'b00};`
31			`state <= BYTE_RTS2;`
32			`end`
33			`else if (dhit) begin`
34	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
35	5	robfinch	`radr2LSB <= sp_inc[1:0];`
36			`sp <= sp_inc;`
37			`pc[7:0] <= rdat8;`
38			`state <= BYTE_RTS3;`
39			`end`
40			`else`
41			dmiss <= `TRUE;
42			`BYTE_RTS2:`
43			`if (ack_i) begin`
44			`cyc_o <= 1'b0;`
45			`stb_o <= 1'b0;`
46			`sel_o <= 4'h0;`
47			`adr_o <= 34'h0;`
48	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
49	5	robfinch	`radr2LSB <= sp_inc[1:0];`
50			`sp <= sp_inc;`
51			`pc[7:0] <= dati;`
52			`state <= BYTE_RTS3;`
53			`end`
54	21	robfinch	`else if (err_i) begin`
55			`lock_o <= 1'b0;`
56			`cyc_o <= 1'b0;`
57			`stb_o <= 1'b0;`
58			`we_o <= 1'b0;`
59			`sel_o <= 4'h0;`
60			`adr_o <= 34'h0;`
61			`dat_o <= 32'h0;`
62			`state <= BUS_ERROR;`
63			`end`
64	5	robfinch	`BYTE_RTS3:`
65			`if (unCachedData) begin`
66			`cyc_o <= 1'b1;`
67			`stb_o <= 1'b1;`
68			`sel_o <= 4'hF;`
69			`adr_o <= {radr,2'b00};`
70			`state <= BYTE_RTS4;`
71			`end`
72			`else if (dhit) begin`
73			if (ir[7:0]==`RTL) begin
74	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
75	5	robfinch	`radr2LSB <= sp_inc[1:0];`
76			`sp <= sp_inc;`
77			`end`
78			`pc[15:8] <= rdat8;`
79			`state <= BYTE_RTS5;`
80			`end`
81			`else`
82			dmiss <= `TRUE;
83			`BYTE_RTS4:`
84			`if (ack_i) begin`
85			`cyc_o <= 1'b0;`
86			`stb_o <= 1'b0;`
87			`sel_o <= 4'h0;`
88			`adr_o <= 34'h0;`
89			`pc[15:8] <= dati;`
90			if (ir[7:0]==`RTL) begin
91	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
92	5	robfinch	`radr2LSB <= sp_inc[1:0];`
93			`sp <= sp_inc;`
94			`end`
95			`state <= BYTE_RTS5;`
96			`end`
97	21	robfinch	`else if (err_i) begin`
98			`lock_o <= 1'b0;`
99			`cyc_o <= 1'b0;`
100			`stb_o <= 1'b0;`
101			`we_o <= 1'b0;`
102			`sel_o <= 4'h0;`
103			`adr_o <= 34'h0;`
104			`dat_o <= 32'h0;`
105			`state <= BUS_ERROR;`
106			`end`
107	5	robfinch	`BYTE_RTS5:`
108			if (ir[7:0]!=`RTL) begin
109			`pc <= pc + 32'd1;`
110			`state <= IFETCH;`
111			`end`
112			`else begin`
113			`if (unCachedData) begin`
114			`cyc_o <= 1'b1;`
115			`stb_o <= 1'b1;`
116			`sel_o <= 4'hF;`
117			`adr_o <= {radr,2'b00};`
118			`state <= BYTE_RTS6;`
119			`end`
120			`else if (dhit) begin`
121	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
122	5	robfinch	`radr2LSB <= sp_inc[1:0];`
123			`sp <= sp_inc;`
124			`pc[23:16] <= rdat8;`
125			`state <= BYTE_RTS7;`
126			`end`
127			`else`
128			dmiss <= `TRUE;
129			`end`
130			`BYTE_RTS6:`
131			`if (ack_i) begin`
132			`cyc_o <= 1'b0;`
133			`stb_o <= 1'b0;`
134			`sel_o <= 4'h0;`
135			`adr_o <= 34'h0;`
136			`pc[23:16] <= dati;`
137	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
138	5	robfinch	`radr2LSB <= sp_inc[1:0];`
139			`sp <= sp_inc;`
140			`state <= BYTE_RTS7;`
141			`end`
142	21	robfinch	`else if (err_i) begin`
143			`lock_o <= 1'b0;`
144			`cyc_o <= 1'b0;`
145			`stb_o <= 1'b0;`
146			`we_o <= 1'b0;`
147			`sel_o <= 4'h0;`
148			`adr_o <= 34'h0;`
149			`dat_o <= 32'h0;`
150			`state <= BUS_ERROR;`
151			`end`
152	5	robfinch	`BYTE_RTS7:`
153			`if (unCachedData) begin`
154			`cyc_o <= 1'b1;`
155			`stb_o <= 1'b1;`
156			`sel_o <= 4'hF;`
157			`adr_o <= {radr,2'b00};`
158			`state <= BYTE_RTS8;`
159			`end`
160			`else if (dhit) begin`
161			`pc[31:24] <= rdat8;`
162			`state <= BYTE_RTS9;`
163			`end`
164			`else`
165			dmiss <= `TRUE;
166			`BYTE_RTS8:`
167			`if (ack_i) begin`
168			`cyc_o <= 1'b0;`
169			`stb_o <= 1'b0;`
170			`sel_o <= 4'h0;`
171			`adr_o <= 34'h0;`
172			`pc[31:24] <= dati;`
173			`state <= BYTE_RTS9;`
174			`end`
175	21	robfinch	`else if (err_i) begin`
176			`lock_o <= 1'b0;`
177			`cyc_o <= 1'b0;`
178			`stb_o <= 1'b0;`
179			`we_o <= 1'b0;`
180			`sel_o <= 4'h0;`
181			`adr_o <= 34'h0;`
182			`dat_o <= 32'h0;`
183			`state <= BUS_ERROR;`
184			`end`
185	5	robfinch	`BYTE_RTS9:`
186			`begin`
187			`pc <= pc + 32'd1;`
188			`state <= IFETCH;`
189			`end`
190	21	robfinch

Browse

Tools

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rts.v] - Blame information for rev 21