URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rts.v] - Blame information for rev 13

Go to most recent revision | Details | Compare with Previous | View Log


// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
// Eight bit mode RTS/RTL states
//
BYTE_RTS1:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTS2;
        end
        else if (dhit) begin
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[7:0] <= rdat8;
                state <= BYTE_RTS3;
        end
        else
                dmiss <= `TRUE;
BYTE_RTS2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                pc[7:0] <= dati;
                state <= BYTE_RTS3;
        end
BYTE_RTS3:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTS4;
        end
        else if (dhit) begin
                if (ir[7:0]==`RTL) begin
                        radr <= {spage[31:8],sp_inc[7:2]};
                        radr2LSB <= sp_inc[1:0];
                        sp <= sp_inc;
                end
                pc[15:8] <= rdat8;
                state <= BYTE_RTS5;
        end
        else
                dmiss <= `TRUE;
BYTE_RTS4:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                pc[15:8] <= dati;
                if (ir[7:0]==`RTL) begin
                        radr <= {spage[31:8],sp_inc[7:2]};
                        radr2LSB <= sp_inc[1:0];
                        sp <= sp_inc;
                end
                state <= BYTE_RTS5;
        end
BYTE_RTS5:
        if (ir[7:0]!=`RTL) begin
                pc <= pc + 32'd1;
                state <= IFETCH;
        end
        else begin
                if (unCachedData) begin
                        cyc_o <= 1'b1;
                        stb_o <= 1'b1;
                        sel_o <= 4'hF;
                        adr_o <= {radr,2'b00};
                        state <= BYTE_RTS6;
                end
                else if (dhit) begin
                        radr <= {spage[31:8],sp_inc[7:2]};
                        radr2LSB <= sp_inc[1:0];
                        sp <= sp_inc;
                        pc[23:16] <= rdat8;
                        state <= BYTE_RTS7;
                end
                else
                        dmiss <= `TRUE;
        end
BYTE_RTS6:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                pc[23:16] <= dati;
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                state <= BYTE_RTS7;
        end
BYTE_RTS7:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= BYTE_RTS8;
        end
        else if (dhit) begin
                pc[31:24] <= rdat8;
                state <= BYTE_RTS9;
        end
        else
                dmiss <= `TRUE;
BYTE_RTS8:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                pc[31:24] <= dati;
                state <= BYTE_RTS9;
        end
BYTE_RTS9:
        begin
                pc <= pc + 32'd1;
                state <= IFETCH;
        end

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`// Eight bit mode RTS/RTL states`
24			`//`
25			`BYTE_RTS1:`
26			`if (unCachedData) begin`
27			`cyc_o <= 1'b1;`
28			`stb_o <= 1'b1;`
29			`sel_o <= 4'hF;`
30			`adr_o <= {radr,2'b00};`
31			`state <= BYTE_RTS2;`
32			`end`
33			`else if (dhit) begin`
34	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
35	5	robfinch	`radr2LSB <= sp_inc[1:0];`
36			`sp <= sp_inc;`
37			`pc[7:0] <= rdat8;`
38			`state <= BYTE_RTS3;`
39			`end`
40			`else`
41			dmiss <= `TRUE;
42			`BYTE_RTS2:`
43			`if (ack_i) begin`
44			`cyc_o <= 1'b0;`
45			`stb_o <= 1'b0;`
46			`sel_o <= 4'h0;`
47			`adr_o <= 34'h0;`
48	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
49	5	robfinch	`radr2LSB <= sp_inc[1:0];`
50			`sp <= sp_inc;`
51			`pc[7:0] <= dati;`
52			`state <= BYTE_RTS3;`
53			`end`
54			`BYTE_RTS3:`
55			`if (unCachedData) begin`
56			`cyc_o <= 1'b1;`
57			`stb_o <= 1'b1;`
58			`sel_o <= 4'hF;`
59			`adr_o <= {radr,2'b00};`
60			`state <= BYTE_RTS4;`
61			`end`
62			`else if (dhit) begin`
63			if (ir[7:0]==`RTL) begin
64	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
65	5	robfinch	`radr2LSB <= sp_inc[1:0];`
66			`sp <= sp_inc;`
67			`end`
68			`pc[15:8] <= rdat8;`
69			`state <= BYTE_RTS5;`
70			`end`
71			`else`
72			dmiss <= `TRUE;
73			`BYTE_RTS4:`
74			`if (ack_i) begin`
75			`cyc_o <= 1'b0;`
76			`stb_o <= 1'b0;`
77			`sel_o <= 4'h0;`
78			`adr_o <= 34'h0;`
79			`pc[15:8] <= dati;`
80			if (ir[7:0]==`RTL) begin
81	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
82	5	robfinch	`radr2LSB <= sp_inc[1:0];`
83			`sp <= sp_inc;`
84			`end`
85			`state <= BYTE_RTS5;`
86			`end`
87			`BYTE_RTS5:`
88			if (ir[7:0]!=`RTL) begin
89			`pc <= pc + 32'd1;`
90			`state <= IFETCH;`
91			`end`
92			`else begin`
93			`if (unCachedData) begin`
94			`cyc_o <= 1'b1;`
95			`stb_o <= 1'b1;`
96			`sel_o <= 4'hF;`
97			`adr_o <= {radr,2'b00};`
98			`state <= BYTE_RTS6;`
99			`end`
100			`else if (dhit) begin`
101	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
102	5	robfinch	`radr2LSB <= sp_inc[1:0];`
103			`sp <= sp_inc;`
104			`pc[23:16] <= rdat8;`
105			`state <= BYTE_RTS7;`
106			`end`
107			`else`
108			dmiss <= `TRUE;
109			`end`
110			`BYTE_RTS6:`
111			`if (ack_i) begin`
112			`cyc_o <= 1'b0;`
113			`stb_o <= 1'b0;`
114			`sel_o <= 4'h0;`
115			`adr_o <= 34'h0;`
116			`pc[23:16] <= dati;`
117	13	robfinch	`radr <= {spage[31:8],sp_inc[7:2]};`
118	5	robfinch	`radr2LSB <= sp_inc[1:0];`
119			`sp <= sp_inc;`
120			`state <= BYTE_RTS7;`
121			`end`
122			`BYTE_RTS7:`
123			`if (unCachedData) begin`
124			`cyc_o <= 1'b1;`
125			`stb_o <= 1'b1;`
126			`sel_o <= 4'hF;`
127			`adr_o <= {radr,2'b00};`
128			`state <= BYTE_RTS8;`
129			`end`
130			`else if (dhit) begin`
131			`pc[31:24] <= rdat8;`
132			`state <= BYTE_RTS9;`
133			`end`
134			`else`
135			dmiss <= `TRUE;
136			`BYTE_RTS8:`
137			`if (ack_i) begin`
138			`cyc_o <= 1'b0;`
139			`stb_o <= 1'b0;`
140			`sel_o <= 4'h0;`
141			`adr_o <= 34'h0;`
142			`pc[31:24] <= dati;`
143			`state <= BYTE_RTS9;`
144			`end`
145			`BYTE_RTS9:`
146			`begin`
147			`pc <= pc + 32'd1;`
148			`state <= IFETCH;`
149			`end`

Browse

Tools

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rts.v] - Blame information for rev 13