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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rts.v] - Blame information for rev 5

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Line No. Rev Author Line
1 5 robfinch 
// Eight bit mode RTS/RTL states
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//
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BYTE_RTS1:
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        if (unCachedData) begin
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                sel_o <= 4'hF;
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                adr_o <= {radr,2'b00};
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                state <= BYTE_RTS2;
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        end
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        else if (dhit) begin
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                radr <= {26'h1,sp_inc[7:2]};
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                radr2LSB <= sp_inc[1:0];
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                sp <= sp_inc;
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                pc[7:0] <= rdat8;
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                state <= BYTE_RTS3;
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        end
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        else
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                dmiss <= `TRUE;
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BYTE_RTS2:
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        if (ack_i) begin
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                sel_o <= 4'h0;
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                adr_o <= 34'h0;
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                radr <= {26'h1,sp_inc[7:2]};
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                radr2LSB <= sp_inc[1:0];
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                sp <= sp_inc;
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                pc[7:0] <= dati;
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                state <= BYTE_RTS3;
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        end
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BYTE_RTS3:
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        if (unCachedData) begin
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                sel_o <= 4'hF;
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                adr_o <= {radr,2'b00};
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                state <= BYTE_RTS4;
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        end
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        else if (dhit) begin
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                if (ir[7:0]==`RTL) begin
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                        radr <= {26'h1,sp_inc[7:2]};
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                        radr2LSB <= sp_inc[1:0];
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                        sp <= sp_inc;
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                end
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                pc[15:8] <= rdat8;
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                state <= BYTE_RTS5;
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        end
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        else
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                dmiss <= `TRUE;
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BYTE_RTS4:
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        if (ack_i) begin
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                sel_o <= 4'h0;
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                adr_o <= 34'h0;
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                pc[15:8] <= dati;
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                if (ir[7:0]==`RTL) begin
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                        radr <= {26'h1,sp_inc[7:2]};
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                        radr2LSB <= sp_inc[1:0];
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                        sp <= sp_inc;
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                end
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                state <= BYTE_RTS5;
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        end
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BYTE_RTS5:
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        if (ir[7:0]!=`RTL) begin
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                pc <= pc + 32'd1;
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                state <= IFETCH;
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        end
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        else begin
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                if (unCachedData) begin
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                        cyc_o <= 1'b1;
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                        stb_o <= 1'b1;
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                        sel_o <= 4'hF;
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                        adr_o <= {radr,2'b00};
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                        state <= BYTE_RTS6;
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                end
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                else if (dhit) begin
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                        radr <= {26'h1,sp_inc[7:2]};
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                        radr2LSB <= sp_inc[1:0];
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                        sp <= sp_inc;
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                        pc[23:16] <= rdat8;
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                        state <= BYTE_RTS7;
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                end
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                else
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                        dmiss <= `TRUE;
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        end
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BYTE_RTS6:
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        if (ack_i) begin
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                sel_o <= 4'h0;
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                adr_o <= 34'h0;
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                pc[23:16] <= dati;
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                radr <= {26'h1,sp_inc[7:2]};
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                radr2LSB <= sp_inc[1:0];
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                sp <= sp_inc;
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                state <= BYTE_RTS7;
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        end
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BYTE_RTS7:
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        if (unCachedData) begin
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                sel_o <= 4'hF;
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                adr_o <= {radr,2'b00};
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                state <= BYTE_RTS8;
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        end
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        else if (dhit) begin
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                pc[31:24] <= rdat8;
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                state <= BYTE_RTS9;
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        end
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        else
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                dmiss <= `TRUE;
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BYTE_RTS8:
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        if (ack_i) begin
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                sel_o <= 4'h0;
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                adr_o <= 34'h0;
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                pc[31:24] <= dati;
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                state <= BYTE_RTS9;
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        end
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BYTE_RTS9:
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        begin
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                pc <= pc + 32'd1;
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                state <= IFETCH;
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        end

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