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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Blame information for rev 21

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
// Cache controller
// Also takes care of loading the instruction buffer for non-cached access
//
case(cstate)
IDLE:
        begin
                if (!cyc_o) begin
                        // A write to a cacheable address does not cause a cache load
                        if (dmiss) begin
                                isDataCacheLoad <= `TRUE;
                                if (isRMW)
                                        lock_o <= 1'b1;
                                cti_o <= 3'b001;
                                bl_o <= 6'd3;
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                sel_o <= 4'hF;
                                adr_o <= {radr[31:2],4'h0};
                                cstate <= LOAD_DCACHE;
                        end
                        else if (!unCachedInsn && imiss && !hit0) begin
                                isInsnCacheLoad <= `TRUE;
                                bte_o <= 2'b00;
                                cti_o <= 3'd001;
                                bl_o <= 6'd3;
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                sel_o <= 4'hF;
                                adr_o <= {pc[31:4],4'h0};
                                cstate <= LOAD_ICACHE;
                        end
                        else if (!unCachedInsn && imiss && !hit1) begin
                                isInsnCacheLoad <= `TRUE;
                                bte_o <= 2'b00;
                                cti_o <= 3'd001;
                                bl_o <= 6'd3;
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                sel_o <= 4'hF;
                                adr_o <= {pcp8[31:4],4'h0};
                                cstate <= LOAD_ICACHE;
                        end
                        else if (unCachedInsn && imiss) begin
                                bte_o <= 2'b00;
                                cti_o <= 3'b001;
                                bl_o <= 6'd2;
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                sel_o <= 4'hf;
                                adr_o <= {pc[31:2],2'b00};
                                cstate <= LOAD_IBUF1;
                        end
                end
        end
LOAD_DCACHE:
        if (ack_i) begin
                if (adr_o[3:2]==2'b11) begin
                        dmiss <= `FALSE;
                        isDataCacheLoad <= `FALSE;
                        cti_o <= 3'b000;
                        bl_o <= 6'd0;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        sel_o <= 4'h0;
                        adr_o <= 34'h0;
                        cstate <= IDLE;
                end
                adr_o <= adr_o + 34'd4;
        end
        // What to do here
        else if (err_i) begin
                if (adr_o[3:2]==2'b11) begin
                        dmiss <= `FALSE;
                        isDataCacheLoad <= `FALSE;
                        cti_o <= 3'b000;
                        bl_o <= 6'd0;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        sel_o <= 4'h0;
                        adr_o <= 34'h0;
                        cstate <= IDLE;
                        // The state machine will be waiting for a dhit.
                        // Override the next state and send the processor to the bus error state.
                        state <= BUS_ERROR;
                end
                adr_o <= adr_o + 34'd4;
        end
LOAD_ICACHE:
        if (ack_i) begin
                if (adr_o[3:2]==2'b11) begin
                        imiss <= `FALSE;
                        isInsnCacheLoad <= `FALSE;
                        cti_o <= 3'b000;
                        bl_o <= 6'd0;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        sel_o <= 4'h0;
                        adr_o <= 34'd0;
                        cstate <= IDLE;
                end
                adr_o <= adr_o + 34'd4;
        end
        else if (err_i) begin
                if (adr_o[3:2]==2'b11) begin
                        imiss <= `FALSE;
                        isInsnCacheLoad <= `FALSE;
                        cti_o <= 3'b000;
                        bl_o <= 6'd0;
                        cyc_o <= 1'b0;
                        stb_o <= 1'b0;
                        sel_o <= 4'h0;
                        adr_o <= 34'd0;
                        state <= INSN_BUS_ERROR;
                        cstate <= IDLE;
                end
                adr_o <= adr_o + 34'd4;
        end
LOAD_IBUF1:
        if (ack_i|err_i) begin
                case(pc[1:0])
                2'd0:   ibuf <= dat_i;
                2'd1:   ibuf <= dat_i[31:8];
                2'd2:   ibuf <= dat_i[31:16];
                2'd3:   ibuf <= dat_i[31:24];
                endcase
                cstate <= LOAD_IBUF2;
                adr_o <= adr_o + 34'd4;
        end
LOAD_IBUF2:
        if (ack_i|err_i) begin
                case(pc[1:0])
                2'd0:   ibuf[55:32] <= dat_i[23:0];
                2'd1:   ibuf[55:24] <= dat_i;
                2'd2:   ibuf[47:16] <= dat_i;
                2'd3:   ibuf[39:8] <= dat_i;
                endcase
                cstate <= LOAD_IBUF3;
                adr_o <= adr_o + 34'd4;
        end
LOAD_IBUF3:
        if (ack_i) begin
                case(pc[1:0])
                2'd0:   ;
                2'd1:   ;
                2'd2:   ibuf[55:48] <= dat_i[7:0];
                2'd3:   ibuf[55:40] <= dat_i[15:0];
                endcase
                cti_o <= 3'd0;
                bl_o <= 6'd0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'd0;
                cstate <= IDLE;
                imiss <= `FALSE;
                bufadr <= pc;   // clears the miss
        end
        else if (err_i) begin
                case(pc[1:0])
                2'd0:   ;
                2'd1:   ;
                2'd2:   ibuf[55:48] <= dat_i[7:0];
                2'd3:   ibuf[55:40] <= dat_i[15:0];
                endcase
                cti_o <= 3'd0;
                bl_o <= 6'd0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'd0;
                cstate <= IDLE;
                state <= INSN_BUS_ERROR;
                imiss <= `FALSE;
                bufadr <= pc;   // clears the miss
        end
 
endcase

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`// Cache controller`
24			`// Also takes care of loading the instruction buffer for non-cached access`
25			`//`
26			`case(cstate)`
27			`IDLE:`
28			`begin`
29			`if (!cyc_o) begin`
30			`// A write to a cacheable address does not cause a cache load`
31			`if (dmiss) begin`
32			isDataCacheLoad <= `TRUE;
33			`if (isRMW)`
34			`lock_o <= 1'b1;`
35			`cti_o <= 3'b001;`
36			`bl_o <= 6'd3;`
37			`cyc_o <= 1'b1;`
38			`stb_o <= 1'b1;`
39			`sel_o <= 4'hF;`
40			`adr_o <= {radr[31:2],4'h0};`
41			`cstate <= LOAD_DCACHE;`
42			`end`
43			`else if (!unCachedInsn && imiss && !hit0) begin`
44			isInsnCacheLoad <= `TRUE;
45			`bte_o <= 2'b00;`
46			`cti_o <= 3'd001;`
47			`bl_o <= 6'd3;`
48			`cyc_o <= 1'b1;`
49			`stb_o <= 1'b1;`
50			`sel_o <= 4'hF;`
51			`adr_o <= {pc[31:4],4'h0};`
52			`cstate <= LOAD_ICACHE;`
53			`end`
54			`else if (!unCachedInsn && imiss && !hit1) begin`
55			isInsnCacheLoad <= `TRUE;
56			`bte_o <= 2'b00;`
57			`cti_o <= 3'd001;`
58			`bl_o <= 6'd3;`
59			`cyc_o <= 1'b1;`
60			`stb_o <= 1'b1;`
61			`sel_o <= 4'hF;`
62			`adr_o <= {pcp8[31:4],4'h0};`
63			`cstate <= LOAD_ICACHE;`
64			`end`
65			`else if (unCachedInsn && imiss) begin`
66			`bte_o <= 2'b00;`
67			`cti_o <= 3'b001;`
68			`bl_o <= 6'd2;`
69			`cyc_o <= 1'b1;`
70			`stb_o <= 1'b1;`
71			`sel_o <= 4'hf;`
72			`adr_o <= {pc[31:2],2'b00};`
73			`cstate <= LOAD_IBUF1;`
74			`end`
75			`end`
76			`end`
77			`LOAD_DCACHE:`
78			`if (ack_i) begin`
79			`if (adr_o[3:2]==2'b11) begin`
80			dmiss <= `FALSE;
81			isDataCacheLoad <= `FALSE;
82			`cti_o <= 3'b000;`
83			`bl_o <= 6'd0;`
84			`cyc_o <= 1'b0;`
85			`stb_o <= 1'b0;`
86			`sel_o <= 4'h0;`
87			`adr_o <= 34'h0;`
88			`cstate <= IDLE;`
89			`end`
90			`adr_o <= adr_o + 34'd4;`
91			`end`
92	21	robfinch	`// What to do here`
93			`else if (err_i) begin`
94			`if (adr_o[3:2]==2'b11) begin`
95			dmiss <= `FALSE;
96			isDataCacheLoad <= `FALSE;
97			`cti_o <= 3'b000;`
98			`bl_o <= 6'd0;`
99			`cyc_o <= 1'b0;`
100			`stb_o <= 1'b0;`
101			`sel_o <= 4'h0;`
102			`adr_o <= 34'h0;`
103			`cstate <= IDLE;`
104			`// The state machine will be waiting for a dhit.`
105			`// Override the next state and send the processor to the bus error state.`
106			`state <= BUS_ERROR;`
107			`end`
108			`adr_o <= adr_o + 34'd4;`
109			`end`
110	5	robfinch	`LOAD_ICACHE:`
111			`if (ack_i) begin`
112			`if (adr_o[3:2]==2'b11) begin`
113			imiss <= `FALSE;
114			isInsnCacheLoad <= `FALSE;
115			`cti_o <= 3'b000;`
116			`bl_o <= 6'd0;`
117			`cyc_o <= 1'b0;`
118			`stb_o <= 1'b0;`
119			`sel_o <= 4'h0;`
120			`adr_o <= 34'd0;`
121			`cstate <= IDLE;`
122			`end`
123			`adr_o <= adr_o + 34'd4;`
124			`end`
125	21	robfinch	`else if (err_i) begin`
126			`if (adr_o[3:2]==2'b11) begin`
127			imiss <= `FALSE;
128			isInsnCacheLoad <= `FALSE;
129			`cti_o <= 3'b000;`
130			`bl_o <= 6'd0;`
131			`cyc_o <= 1'b0;`
132			`stb_o <= 1'b0;`
133			`sel_o <= 4'h0;`
134			`adr_o <= 34'd0;`
135			`state <= INSN_BUS_ERROR;`
136			`cstate <= IDLE;`
137			`end`
138			`adr_o <= adr_o + 34'd4;`
139			`end`
140	5	robfinch	`LOAD_IBUF1:`
141	21	robfinch	`if (ack_i\|err_i) begin`
142	5	robfinch	`case(pc[1:0])`
143			`2'd0: ibuf <= dat_i;`
144			`2'd1: ibuf <= dat_i[31:8];`
145			`2'd2: ibuf <= dat_i[31:16];`
146			`2'd3: ibuf <= dat_i[31:24];`
147			`endcase`
148			`cstate <= LOAD_IBUF2;`
149			`adr_o <= adr_o + 34'd4;`
150			`end`
151			`LOAD_IBUF2:`
152	21	robfinch	`if (ack_i\|err_i) begin`
153	5	robfinch	`case(pc[1:0])`
154			`2'd0: ibuf[55:32] <= dat_i[23:0];`
155	20	robfinch	`2'd1: ibuf[55:24] <= dat_i;`
156			`2'd2: ibuf[47:16] <= dat_i;`
157	5	robfinch	`2'd3: ibuf[39:8] <= dat_i;`
158			`endcase`
159			`cstate <= LOAD_IBUF3;`
160			`adr_o <= adr_o + 34'd4;`
161			`end`
162			`LOAD_IBUF3:`
163			`if (ack_i) begin`
164			`case(pc[1:0])`
165			`2'd0: ;`
166			`2'd1: ;`
167			`2'd2: ibuf[55:48] <= dat_i[7:0];`
168			`2'd3: ibuf[55:40] <= dat_i[15:0];`
169			`endcase`
170			`cti_o <= 3'd0;`
171			`bl_o <= 6'd0;`
172			`cyc_o <= 1'b0;`
173			`stb_o <= 1'b0;`
174			`sel_o <= 4'h0;`
175			`adr_o <= 34'd0;`
176			`cstate <= IDLE;`
177			imiss <= `FALSE;
178			`bufadr <= pc; // clears the miss`
179			`end`
180	21	robfinch	`else if (err_i) begin`
181			`case(pc[1:0])`
182			`2'd0: ;`
183			`2'd1: ;`
184			`2'd2: ibuf[55:48] <= dat_i[7:0];`
185			`2'd3: ibuf[55:40] <= dat_i[15:0];`
186			`endcase`
187			`cti_o <= 3'd0;`
188			`bl_o <= 6'd0;`
189			`cyc_o <= 1'b0;`
190			`stb_o <= 1'b0;`
191			`sel_o <= 4'h0;`
192			`adr_o <= 34'd0;`
193			`cstate <= IDLE;`
194			`state <= INSN_BUS_ERROR;`
195			imiss <= `FALSE;
196			`bufadr <= pc; // clears the miss`
197			`end`
198
199	5	robfinch	`endcase`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Blame information for rev 21