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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Blame information for rev 35

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2013  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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// Cache controller
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// Also takes care of loading the instruction buffer for non-cached access
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//
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`ifdef SUPPORT_DCACHE
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DCACHE1:
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        begin
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                isDataCacheLoad <= `TRUE;
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                if (isRMW)
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                        lock_o <= 1'b1;
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                wb_burst(6'd3,{radr[31:2],4'h0});
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                state <= LOAD_DCACHE;
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        end
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LOAD_DCACHE:
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        if (ack_i) begin
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                if (adr_o[3:2]==2'b10)
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                        cti_o <= 3'b111;
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                if (adr_o[3:2]==2'b11) begin
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                        dmiss <= `FALSE;
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                        isDataCacheLoad <= `FALSE;
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                        wb_nack();
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                        state <= retstate;
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                end
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                adr_o[3:2] <= adr_o[3:2] + 2'd1;
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        end
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`ifdef SUPPORT_BERR
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        else if (err_i) begin
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                if (adr_o[3:2]==2'b10)
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                        cti_o <= 3'b111;
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                if (adr_o[3:2]==2'b11) begin
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                        dmiss <= `FALSE;
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                        isDataCacheLoad <= `FALSE;
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                        wb_nack();
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                        // The state machine will be waiting for a dhit.
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                        // Override the next state and send the processor to the bus error state.
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                        intno <= 9'd508;
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                        state <= BUS_ERROR;
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                end
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                derr_address <= adr_o[33:2];
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                adr_o[3:2] <= adr_o[3:2] + 2'd1;
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        end
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`endif
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`endif
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`ifdef SUPPORT_ICACHE
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ICACHE1:
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        if (!hit0) begin
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                isInsnCacheLoad <= `TRUE;
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                wb_burst(6'd3,{pc[31:4],4'h0});
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                state <= LOAD_ICACHE;
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        end
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        else if (!hit1) begin
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                isInsnCacheLoad <= `TRUE;
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                wb_burst(6'd3,{pcp8[31:4],4'h0});
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                state <= LOAD_ICACHE;
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        end
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        else
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                state <= em ? BYTE_IFETCH : IFETCH;
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LOAD_ICACHE:
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        if (ack_i) begin
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                if (adr_o[3:2]==2'b10)
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                        cti_o <= 3'b111;
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                if (adr_o[3:2]==2'b11) begin
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                        isInsnCacheLoad <= `FALSE;
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                        wb_nack();
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`ifdef ICACHE_2WAY
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                        clfsr <= {clfsr,clfsr_fb};
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`endif
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                        state <= ICACHE1;
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                end
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                adr_o[3:2] <= adr_o[3:2] + 2'd1;
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        end
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`ifdef SUPPORT_BERR
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        else if (err_i) begin
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                if (adr_o[3:2]==2'b10)
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                        cti_o <= 3'b111;
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                if (adr_o[3:2]==2'b11) begin
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                        isInsnCacheLoad <= `FALSE;
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                        wb_nack();
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                        derr_address <= 32'd0;
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                        intno <= 9'd509;
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                        state <= BUS_ERROR;
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`ifdef ICACHE_2WAY
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                        clfsr <= {clfsr,clfsr_fb};
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`endif
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                end
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                adr_o[3:2] <= adr_o[3:2] + 2'd1;
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        end
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`endif
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`endif
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LOAD_IBUF1:
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        if (!cyc_o) begin
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                // Emulation mode never needs to read more than two words.
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                // Native mode might need up to three words.
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                wb_burst((em ? 6'd1: 6'd2),{pc[31:2],2'b00});
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        end
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        else if (ack_i|err_i) begin
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                if (em)
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                        cti_o <= 3'b111;
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                case(pc[1:0])
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                2'd0:   ibuf <= dat_i;
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                2'd1:   ibuf <= dat_i[31:8];
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                2'd2:   ibuf <= dat_i[31:16];
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                2'd3:   ibuf <= dat_i[31:24];
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                endcase
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                state <= LOAD_IBUF2;
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        end
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LOAD_IBUF2:
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        if (ack_i|err_i) begin
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                state <= em ? BYTE_IFETCH : LOAD_IBUF3;
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                case(pc[1:0])
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                2'd0:   ibuf[55:32] <= dat_i[23:0];
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                2'd1:   ibuf[55:24] <= dat_i;
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                2'd2:   ibuf[47:16] <= dat_i;
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                2'd3:   ibuf[39:8] <= dat_i;
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                endcase
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                if (em) begin
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                        wb_nack();
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                        if (err_i) begin
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                                derr_address <= 32'd0;
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                                intno <= 9'd509;
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                                state <= BUS_ERROR;
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                        end
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                        bufadr <= pc;   // clears the miss
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                end
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                else
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                        cti_o <= 3'b111;
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        end
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LOAD_IBUF3:
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        if (ack_i) begin
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                wb_nack();
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                case(pc[1:0])
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                2'd0:   ;
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                2'd1:   ;
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                2'd2:   ibuf[55:48] <= dat_i[7:0];
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                2'd3:   ibuf[55:40] <= dat_i[15:0];
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                endcase
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                state <= IFETCH;
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                bufadr <= pc;   // clears the miss
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        end
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`ifdef SUPPORT_BERR
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        else if (err_i) begin
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                wb_nack();
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                case(pc[1:0])
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                2'd0:   ;
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                2'd1:   ;
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                2'd2:   ibuf[55:48] <= dat_i[7:0];
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                2'd3:   ibuf[55:40] <= dat_i[15:0];
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                endcase
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                derr_address <= 32'd0;
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                intno <= 9'd509;
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                state <= BUS_ERROR;
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                bufadr <= pc;   // clears the miss
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        end
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`endif

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