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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Blame information for rev 39

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
// Cache controller
// Also takes care of loading the instruction buffer for non-cached access
//
`ifdef SUPPORT_DCACHE
DCACHE1:
        begin
                isDataCacheLoad <= `TRUE;
                if (isRMW)
                        lock_o <= 1'b1;
                wb_burst(6'd3,{radr[31:2],4'h0});
                state <= LOAD_DCACHE;
        end
LOAD_DCACHE:
        if (ack_i) begin
                if (adr_o[3:2]==2'b10)
                        cti_o <= 3'b111;
                if (adr_o[3:2]==2'b11) begin
                        dmiss <= `FALSE;
                        isDataCacheLoad <= `FALSE;
                        wb_nack();
                        state <= retstate;
                end
                adr_o[3:2] <= adr_o[3:2] + 2'd1;
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                if (adr_o[3:2]==2'b10)
                        cti_o <= 3'b111;
                if (adr_o[3:2]==2'b11) begin
                        dmiss <= `FALSE;
                        isDataCacheLoad <= `FALSE;
                        wb_nack();
                        // The state machine will be waiting for a dhit.
                        // Override the next state and send the processor to the bus error state.
                        intno <= 9'd508;
                        state <= BUS_ERROR;
                end
                derr_address <= adr_o[33:2];
                adr_o[3:2] <= adr_o[3:2] + 2'd1;
        end
`endif
`endif
`ifdef SUPPORT_ICACHE
ICACHE1:
        if (!hit0) begin
                isInsnCacheLoad <= `TRUE;
                wb_burst(6'd3,{pc[31:4],4'h0});
                state <= LOAD_ICACHE;
        end
        else if (!hit1) begin
                isInsnCacheLoad <= `TRUE;
                wb_burst(6'd3,{pcp8[31:4],4'h0});
                state <= LOAD_ICACHE;
        end
        else
                state <= ic_whence;     // return to where we came from
LOAD_ICACHE:
        if (ack_i) begin
                if (adr_o[3:2]==2'b10)
                        cti_o <= 3'b111;
                if (adr_o[3:2]==2'b11) begin
                        isInsnCacheLoad <= `FALSE;
                        wb_nack();
`ifdef ICACHE_2WAY
                        clfsr <= {clfsr,clfsr_fb};
`endif
                        state <= ICACHE1;
                end
                adr_o[3:2] <= adr_o[3:2] + 2'd1;
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                if (adr_o[3:2]==2'b10)
                        cti_o <= 3'b111;
                if (adr_o[3:2]==2'b11) begin
                        isInsnCacheLoad <= `FALSE;
                        wb_nack();
                        derr_address <= 32'd0;
                        intno <= 9'd509;
                        state <= BUS_ERROR;
`ifdef ICACHE_2WAY
                        clfsr <= {clfsr,clfsr_fb};
`endif
                end
                adr_o[3:2] <= adr_o[3:2] + 2'd1;
        end
`endif
`endif
 
LOAD_IBUF1:
        if (!cyc_o) begin
                // Emulation mode never needs to read more than two words.
                // Native mode might need up to three words.
                wb_burst((em ? 6'd1: 6'd2),{pc[31:2],2'b00});
        end
        else if (ack_i|err_i) begin
                if (em)
                        cti_o <= 3'b111;
                case(pc[1:0])
                2'd0:   ibuf <= dat_i;
                2'd1:   ibuf <= dat_i[31:8];
                2'd2:   ibuf <= dat_i[31:16];
                2'd3:   ibuf <= dat_i[31:24];
                endcase
                state <= LOAD_IBUF2;
        end
LOAD_IBUF2:
        if (ack_i|err_i) begin
                state <= ic_whence==BYTE_IFETCH ? BYTE_IFETCH : LOAD_IBUF3;
                case(pc[1:0])
                2'd0:   ibuf[55:32] <= dat_i[23:0];
                2'd1:   ibuf[55:24] <= dat_i;
                2'd2:   ibuf[47:16] <= dat_i;
                2'd3:   ibuf[39:8] <= dat_i;
                endcase
                if (em) begin
                        wb_nack();
                        if (err_i) begin
                                derr_address <= 32'd0;
                                intno <= 9'd509;
                                state <= BUS_ERROR;
                        end
                        bufadr <= pc;   // clears the miss
                end
                else
                        cti_o <= 3'b111;
        end
LOAD_IBUF3:
        if (ack_i) begin
                wb_nack();
                case(pc[1:0])
                2'd0:   ;
                2'd1:   ;
                2'd2:   ibuf[55:48] <= dat_i[7:0];
                2'd3:   ibuf[55:40] <= dat_i[15:0];
                endcase
                state <= IFETCH;
                bufadr <= pc;   // clears the miss
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                wb_nack();
                case(pc[1:0])
                2'd0:   ;
                2'd1:   ;
                2'd2:   ibuf[55:48] <= dat_i[7:0];
                2'd3:   ibuf[55:40] <= dat_i[15:0];
                endcase
                derr_address <= 32'd0;
                intno <= 9'd509;
                state <= BUS_ERROR;
                bufadr <= pc;   // clears the miss
        end
`endif

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5	35	robfinch	`// \/_// robfinch<remove>@finitron.ca`
6	10	robfinch	`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`// Cache controller`
24			`// Also takes care of loading the instruction buffer for non-cached access`
25			`//`
26	32	robfinch	`ifdef SUPPORT_DCACHE
27			`DCACHE1:`
28	5	robfinch	`begin`
29	32	robfinch	isDataCacheLoad <= `TRUE;
30			`if (isRMW)`
31			`lock_o <= 1'b1;`
32	35	robfinch	`wb_burst(6'd3,{radr[31:2],4'h0});`
33	32	robfinch	`state <= LOAD_DCACHE;`
34	5	robfinch	`end`
35			`LOAD_DCACHE:`
36			`if (ack_i) begin`
37	35	robfinch	`if (adr_o[3:2]==2'b10)`
38			`cti_o <= 3'b111;`
39	5	robfinch	`if (adr_o[3:2]==2'b11) begin`
40			dmiss <= `FALSE;
41			isDataCacheLoad <= `FALSE;
42	35	robfinch	`wb_nack();`
43	32	robfinch	`state <= retstate;`
44	5	robfinch	`end`
45	32	robfinch	`adr_o[3:2] <= adr_o[3:2] + 2'd1;`
46	5	robfinch	`end`
47	30	robfinch	`ifdef SUPPORT_BERR
48	21	robfinch	`else if (err_i) begin`
49	35	robfinch	`if (adr_o[3:2]==2'b10)`
50			`cti_o <= 3'b111;`
51	21	robfinch	`if (adr_o[3:2]==2'b11) begin`
52			dmiss <= `FALSE;
53			isDataCacheLoad <= `FALSE;
54	35	robfinch	`wb_nack();`
55	21	robfinch	`// The state machine will be waiting for a dhit.`
56			`// Override the next state and send the processor to the bus error state.`
57	35	robfinch	`intno <= 9'd508;`
58	21	robfinch	`state <= BUS_ERROR;`
59			`end`
60	35	robfinch	`derr_address <= adr_o[33:2];`
61	32	robfinch	`adr_o[3:2] <= adr_o[3:2] + 2'd1;`
62	21	robfinch	`end`
63	30	robfinch	`endif
64			`endif
65			`ifdef SUPPORT_ICACHE
66	32	robfinch	`ICACHE1:`
67			`if (!hit0) begin`
68			isInsnCacheLoad <= `TRUE;
69	35	robfinch	`wb_burst(6'd3,{pc[31:4],4'h0});`
70	32	robfinch	`state <= LOAD_ICACHE;`
71			`end`
72			`else if (!hit1) begin`
73			isInsnCacheLoad <= `TRUE;
74	35	robfinch	`wb_burst(6'd3,{pcp8[31:4],4'h0});`
75	32	robfinch	`state <= LOAD_ICACHE;`
76			`end`
77			`else`
78	38	robfinch	`state <= ic_whence; // return to where we came from`
79	5	robfinch	`LOAD_ICACHE:`
80			`if (ack_i) begin`
81	35	robfinch	`if (adr_o[3:2]==2'b10)`
82			`cti_o <= 3'b111;`
83	5	robfinch	`if (adr_o[3:2]==2'b11) begin`
84			isInsnCacheLoad <= `FALSE;
85	35	robfinch	`wb_nack();`
86	32	robfinch	`ifdef ICACHE_2WAY
87			`clfsr <= {clfsr,clfsr_fb};`
88			`endif
89			`state <= ICACHE1;`
90	5	robfinch	`end`
91	32	robfinch	`adr_o[3:2] <= adr_o[3:2] + 2'd1;`
92	5	robfinch	`end`
93	30	robfinch	`ifdef SUPPORT_BERR
94	21	robfinch	`else if (err_i) begin`
95	35	robfinch	`if (adr_o[3:2]==2'b10)`
96			`cti_o <= 3'b111;`
97	21	robfinch	`if (adr_o[3:2]==2'b11) begin`
98			isInsnCacheLoad <= `FALSE;
99	35	robfinch	`wb_nack();`
100			`derr_address <= 32'd0;`
101			`intno <= 9'd509;`
102			`state <= BUS_ERROR;`
103	32	robfinch	`ifdef ICACHE_2WAY
104			`clfsr <= {clfsr,clfsr_fb};`
105			`endif
106	21	robfinch	`end`
107	32	robfinch	`adr_o[3:2] <= adr_o[3:2] + 2'd1;`
108	21	robfinch	`end`
109	30	robfinch	`endif
110			`endif
111	35	robfinch
112	5	robfinch	`LOAD_IBUF1:`
113	32	robfinch	`if (!cyc_o) begin`
114	35	robfinch	`// Emulation mode never needs to read more than two words.`
115			`// Native mode might need up to three words.`
116			`wb_burst((em ? 6'd1: 6'd2),{pc[31:2],2'b00});`
117	32	robfinch	`end`
118			`else if (ack_i\|err_i) begin`
119	35	robfinch	`if (em)`
120			`cti_o <= 3'b111;`
121	5	robfinch	`case(pc[1:0])`
122			`2'd0: ibuf <= dat_i;`
123			`2'd1: ibuf <= dat_i[31:8];`
124			`2'd2: ibuf <= dat_i[31:16];`
125			`2'd3: ibuf <= dat_i[31:24];`
126			`endcase`
127	32	robfinch	`state <= LOAD_IBUF2;`
128	5	robfinch	`end`
129			`LOAD_IBUF2:`
130	21	robfinch	`if (ack_i\|err_i) begin`
131	38	robfinch	`state <= ic_whence==BYTE_IFETCH ? BYTE_IFETCH : LOAD_IBUF3;`
132	5	robfinch	`case(pc[1:0])`
133			`2'd0: ibuf[55:32] <= dat_i[23:0];`
134	20	robfinch	`2'd1: ibuf[55:24] <= dat_i;`
135			`2'd2: ibuf[47:16] <= dat_i;`
136	5	robfinch	`2'd3: ibuf[39:8] <= dat_i;`
137			`endcase`
138	35	robfinch	`if (em) begin`
139			`wb_nack();`
140			`if (err_i) begin`
141			`derr_address <= 32'd0;`
142			`intno <= 9'd509;`
143			`state <= BUS_ERROR;`
144			`end`
145			`bufadr <= pc; // clears the miss`
146			`end`
147			`else`
148			`cti_o <= 3'b111;`
149	5	robfinch	`end`
150			`LOAD_IBUF3:`
151			`if (ack_i) begin`
152	35	robfinch	`wb_nack();`
153	5	robfinch	`case(pc[1:0])`
154			`2'd0: ;`
155			`2'd1: ;`
156			`2'd2: ibuf[55:48] <= dat_i[7:0];`
157			`2'd3: ibuf[55:40] <= dat_i[15:0];`
158			`endcase`
159	32	robfinch	`state <= IFETCH;`
160	5	robfinch	`bufadr <= pc; // clears the miss`
161			`end`
162	30	robfinch	`ifdef SUPPORT_BERR
163	21	robfinch	`else if (err_i) begin`
164	35	robfinch	`wb_nack();`
165	21	robfinch	`case(pc[1:0])`
166			`2'd0: ;`
167			`2'd1: ;`
168			`2'd2: ibuf[55:48] <= dat_i[7:0];`
169			`2'd3: ibuf[55:40] <= dat_i[15:0];`
170			`endcase`
171	35	robfinch	`derr_address <= 32'd0;`
172			`intno <= 9'd509;`
173			`state <= BUS_ERROR;`
174	21	robfinch	`bufadr <= pc; // clears the miss`
175			`end`
176	30	robfinch	`endif

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Blame information for rev 39