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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
task decode_tsk;
        begin
                first_ifetch <= `TRUE;
                Rt <= 4'h0;             // Default
                state <= IFETCH;
                pc <= pc + pc_inc;
                pc_inc2 <= pc_inc;
                a <= rfoa;
                res <= alu_out;
                ttrig <= tf;
                oisp <= isp;    // for bus retry
                // This case statement should include all opcodes or the opcode
                // will end up being treated as an undefined operation.
                case(ir9)
                `STP:   clk_en <= 1'b0;
                `NOP:   ;
//                              casex(ir[63:0])
//                              {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}:      pc <= pcp8;
//                              {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}:     pc <= pcp7;
//                              {16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}:       pc <= pcp6;
//                              {24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}:  pc <= pcp5;
//                              {32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}:     pc <= pcp4;
//                              {40'hxxxxxxxxxx,`NOP,`NOP,`NOP}:        pc <= pcp3;
//                              {48'hxxxxxxxxxxxx,`NOP,`NOP}:   pc <= pcp2;
//                              {56'hxxxxxxxxxxxxxx,`NOP}:      pc <= pcp1;
//                              endcase
                `CLC:   cf <= 1'b0;
                `SEC:   cf <= 1'b1;
                `CLV:   vf <= 1'b0;
                `CLI:   im <= 1'b0;
                `CLD:   df <= 1'b0;
                `SED:   df <= 1'b1;
                `SEI:   im <= 1'b1;
                `WAI:   wai <= 1'b1;
                `TON:   tf <= 1'b1;
                `TOFF:  tf <= 1'b0;
                `HOFF:  hist_capture <= 1'b0;
                // Switching to 65c02 mode zeros out the upper part of the index registers.
                // Switching to 65c816 mode does not zero out the upper part of the index registers,
                // this is unlike switching from '02 to '816 mode. Also, the register size select
                // bits are not affected.
                `XCE:   begin
                                        em <= 1'b1;
                                        m816 <= ~cf;
                                        cf <= ~m816;
                                        if (cf) begin
                                                x[31:8] <= 24'd0;
                                                y[31:8] <= 24'd0;
                                        end
`ifdef SUPPORT_EM8
                                        next_state(BYTE_IFETCH);
`endif
                                end
                `DEX:   Rt <= 4'd2;
                                        // DEX/BNE accelerator
//                                      if (ir[15:8]==`BNE) begin
//                                              if (x!=32'd1) begin
//                                                      if (ir[23:16]==8'h01)
//                                                              pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1;
//                                                      else
//                                                              pc <= pc + {{24{ir[23]}},ir[23:16]} + 32'd1;
//                                              end
//                                              else begin
//                                                      if (ir[23:16]==8'h01)
//                                                              pc <= pcp5;
//                                                      else
//                                                              pc <= pcp3;
//                                              end
//                                      end
                `INX:   Rt <= 4'd2;
                `DEY:   Rt <= 4'd3;
                `INY:   Rt <= 4'd3;
                `DEA:   Rt <= 4'd1;
                `INA:   Rt <= 4'd1;
                `TSX:   Rt <= 4'd2;
                `TSA:   Rt <= 4'd1;
                `TXS:   ;
                `TXA:   Rt <= 4'd1;
                `TXY:   Rt <= 4'd3;
                `TAX:   Rt <= 4'd2;
                `TAY:   Rt <= 4'd3;
                `TAS:   ;
                `TYA:   Rt <= 4'd1;
                `TYX:   Rt <= 4'd2;
                `TRS:           ;
                `TSR:           begin
                                                Rt <= ir[15:12];
                                                case(ir[11:8])
                                                4'h0:   ;
                                                4'h2:   ;
                                                4'h3:   ;
                                                4'h4:   ;
                                                4'h5:   lfsr <= {lfsr[30:0],lfsr_fb};
                                                4'd7:   ;
                                                4'h8:   ;
                                                4'h9:   ;
`ifdef DEBUG
                                                4'hA:   history_ndx <= history_ndx + 6'd1;
`endif
                                                4'hE:   ;
                                                4'hF:   ;
                                                default:        ;
                                                endcase
                                        end
                `ASL_ACC:       Rt <= 4'd1;
                `ROL_ACC:       Rt <= 4'd1;
                `LSR_ACC:       Rt <= 4'd1;
                `ROR_ACC:       Rt <= 4'd1;
 
                `RR:
                        begin
                                Rt <= ir[19:16];
                                case(ir[23:20])
                                `ADD_RR:        b <= rfob;
                                `SUB_RR:        b <= rfob;
                                `AND_RR:        b <= rfob;      // for bit flags
                                `OR_RR:         b <= rfob;
                                `EOR_RR:        b <= rfob;
                                `MUL_RR:        begin b <= rfob; state <= MULDIV1; end
                                `MULS_RR:       begin b <= rfob; state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                                `DIV_RR:        begin b <= rfob; state <= MULDIV1; end
                                `DIVS_RR:       begin b <= rfob; state <= MULDIV1; end
                                `MOD_RR:        begin b <= rfob; state <= MULDIV1; end
                                `MODS_RR:       begin b <= rfob; state <= MULDIV1; end
`endif
`ifdef SUPPORT_SHIFT
                                `ASL_RRR:       begin b <= rfob; state <= CALC; end
                                `LSR_RRR:       begin b <= rfob; state <= CALC; end
`endif
                                default:
                                        begin
                                                Rt <= 4'h0;
                                                pg2 <= `FALSE;
                                                ir <= {8{`BRK}};
                                                hwi <= `TRUE;
                                                vect <= {vbr[31:9],9'd495,2'b00};
                                                pc <= pc;               // override the pc increment
                                                state <= DECODE;
                                        end
                                endcase
                        end
                `LD_RR:         Rt <= ir[15:12];
                `ASL_RR:        Rt <= ir[15:12];
                `ROL_RR:        Rt <= ir[15:12];
                `LSR_RR:        Rt <= ir[15:12];
                `ROR_RR:        Rt <= ir[15:12];
                `DEC_RR:        Rt <= ir[15:12];
                `INC_RR:        Rt <= ir[15:12];
/*
                Can't P&R this
                `ADD_R:         begin Rt <= ir[11: 8]; b <= rfob; end
                `SUB_R:         begin Rt <= ir[11: 8]; b <= rfob; end
                `OR_R:          begin Rt <= ir[11: 8]; b <= rfob; end
                `AND_R:         begin Rt <= ir[11: 8]; b <= rfob; end
                `EOR_R:         begin Rt <= ir[11: 8]; b <= rfob; end
*/
                `ADD_IMM4:      begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
                `SUB_IMM4:      begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
                `OR_IMM4:       begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
                `AND_IMM4:      begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
                `EOR_IMM4:      begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
 
                `ADD_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
                `SUB_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
                `MUL_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                `DIV_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
                `MOD_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
`endif
                `OR_IMM8:       begin Rt <= ir[15:12]; end
                `AND_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
                `EOR_IMM8:      begin Rt <= ir[15:12]; end
                `CMP_IMM8:      ;
`ifdef SUPPORT_SHIFT
                `ASL_IMM8:      begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
                `LSR_IMM8:      begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
`endif
 
                `ADD_IMM16:     begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
                `SUB_IMM16:     begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
                `MUL_IMM16:     begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                `DIV_IMM16:     begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
                `MOD_IMM16:     begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
`endif
                `OR_IMM16:      begin Rt <= ir[15:12]; end
                `AND_IMM16:     begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
                `EOR_IMM16:     begin Rt <= ir[15:12]; end
 
                `ADD_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; end
                `SUB_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; end
                `MUL_IMM16:     begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                `DIV_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
                `MOD_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
`endif
                `OR_IMM32:      begin Rt <= ir[15:12]; end
                `AND_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; end
                `EOR_IMM32:     begin Rt <= ir[15:12]; end
 
                `LDA_IMM32:     Rt <= 4'd1;
                `LDX_IMM32:     Rt <= 4'd2;
                `LDY_IMM32: Rt <= 4'd3;
                `LDA_IMM16:     Rt <= 4'd1;
                `LDX_IMM16: Rt <= 4'd2;
                `LDA_IMM8: Rt <= 4'd1;
                `LDX_IMM8: Rt <= 4'd2;
 
                `SUB_SP8:       ;
                `SUB_SP16:      ;
                `SUB_SP32:      ;
 
                `CPX_IMM32:     ;
                `CPY_IMM32:     ;
 
                `LDX_ZPX:
                        begin
                                Rt <= 4'd2;
                                radr <= zpx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `LDY_ZPX:
                        begin
                                Rt <= 4'd3;
                                radr <= zpx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `ORB_ZPX:
                        begin
                                Rt <= ir[19:16];
                                radr <= zpx32_address[31:2];
                                radr2LSB <= zpx32_address[1:0];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LDX_ABS:
                        begin
                                Rt <= 4'd2;
                                radr <= ir[39:8];
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `LDY_ABS:
                        begin
                                Rt <= 4'd3;
                                radr <= ir[39:8];
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `ORB_ABS:
                        begin
                                Rt <= ir[15:12];
                                radr <= ir[47:18];
                                radr2LSB <= ir[17:16];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LDX_ABSY:
                        begin
                                Rt <= 4'd2;
                                radr <= absx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `LDY_ABSX:
                        begin
                                Rt <= 4'd3;
                                radr <= absx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `ORB_ABSX:
                        begin
                                Rt <= ir[19:16];
                                radr <= absx32_address[31:2];
                                radr2LSB <= absx32_address[1:0];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ST_ZPX:
                        begin
                                wadr <= zpx32_address;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `STB_ZPX:
                        begin
                                wadr <= zpx32_address[31:2];
                                wadr2LSB <= zpx32_address[1:0];
                                store_what <= `STW_RFA8;
                                state <= STORE1;
                        end
                `ST_DSP:
                        begin
                                wadr <= {24'b0,ir[23:16]} + isp;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `ST_ABS:
                        begin
                                wadr <= ir[47:16];
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `STB_ABS:
                        begin
                                wadr <= ir[47:18];
                                wadr2LSB <= ir[17:16];
                                store_what <= `STW_RFA8;
                                state <= STORE1;
                        end
                `ST_ABSX:
                        begin
                                wadr <= absx32_address;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `STB_ABSX:
                        begin
                                wadr <= absx32_address[31:2];
                                wadr2LSB <= absx32_address[1:0];
                                store_what <= `STW_RFA8;
                                state <= STORE1;
                        end
                `STX_ZPX:
                        begin
                                wadr <= zpx32xy_address;
                                store_what <= `STW_X;
                                state <= STORE1;
                        end
                `STX_ABS:
                        begin
                                wadr <= ir[39:8];
                                store_what <= `STW_X;
                                state <= STORE1;
                        end
                `STY_ZPX:
                        begin
                                wadr <= zpx32xy_address;
                                store_what <= `STW_Y;
                                state <= STORE1;
                        end
                `STY_ABS:
                        begin
                                wadr <= ir[39:8];
                                store_what <= `STW_Y;
                                state <= STORE1;
                        end
                `ADD_ZPX,`SUB_ZPX,`AND_ZPX,`TRB_ZPX:
                        begin
                                Rt <= ir[19:16];
                                radr <= zpx32_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LEA_ZPX:
                        begin
                                Rt <= ir[19:16];
                                res <= zpx32_address;
                                state <= IFETCH;
                        end
                // Trim a clock cycle off of loads by testing for Ra = 0.
                `OR_ZPX,`EOR_ZPX,`TSB_ZPX:
                        begin
                                Rt <= ir[19:16];
                                radr <= zpx32_address;
                                load_what <= (Ra==4'd0) ? `WORD_311: `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BMS_ZPX,`BMC_ZPX,`BMF_ZPX,`BMT_ZPX:
                        begin
                                radr <= zpx32xy_address + acc[31:5];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LEA_DSP:
                        begin
                                Rt <= ir[15:12];
                                res <= {24'b0,ir[23:16]} + isp;
                                state <= IFETCH;
                        end
                `ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
                        begin
                                Rt <= ir[15:12];
                                radr <= {24'b0,ir[23:16]} + isp;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX,`LEA_IX:
                        begin
                                if (ir[7:0]!=`ST_IX)     // for ST_IX, Rt=0
                                        Rt <= ir[19:16];
                                radr <= zpx32_address;
                                load_what <= `IA_310;
                                store_what <= `STW_A;
                                state <= LOAD_MAC1;
                        end
                `LEA_RIND:
                        begin
                                Rt <= ir[19:16];
                                res <= rfob;
                                state <= IFETCH;
                        end
                `ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
                        begin
                                radr <= rfob;
                                Rt <= ir[19:16];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ST_RIND:
                        begin
                                wadr <= rfob;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY,`LEA_IY:
                        begin
                                if (ir[7:0]!=`ST_IY)     // for ST_IY, Rt=0
                                        Rt <= ir[19:16];
                                isIY <= 1'b1;
                                radr <= ir[31:20];
                                load_what <= `IA_310;
                                store_what <= `STW_A;
                                state <= LOAD_MAC1;
                        end
                `LEA_ABS:
                        begin
                                res <= ir[47:16];
                                Rt <= ir[15:12];
                                state <= IFETCH;
                        end
                `OR_ABS,`EOR_ABS,`TSB_ABS:
                        begin
                                radr <= ir[47:16];
                                Rt <= ir[15:12];
                                load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ADD_ABS,`SUB_ABS,`AND_ABS,`TRB_ABS:
                        begin
                                radr <= ir[47:16];
                                Rt <= ir[15:12];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `SPL_ABS:
                        begin
                                Rt <= 4'h0;
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS:
                        begin
                                radr <= ir[39:8] + acc[31:5];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LEA_ABSX:
                        begin
                                res <= absx32_address;
                                Rt <= ir[19:16];
                                state <= IFETCH;
                        end
                `ADD_ABSX,`SUB_ABSX,`AND_ABSX:
                        begin
                                radr <= absx32_address;
                                Rt <= ir[19:16];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `OR_ABSX,`EOR_ABSX:
                        begin
                                radr <= absx32_address;
                                Rt <= ir[19:16];
                                load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
                        begin
                                radr <= absx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BMS_ABSX,`BMC_ABSX,`BMF_ABSX,`BMT_ABSX:
                        begin
                                radr <= absx32xy_address + acc[31:5];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `SPL_ABSX:
                        begin
                                Rt <= 4'h0;
                                radr <= absx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
 
                `CPX_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `CPY_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `CPX_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `CPY_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BRK:
                        begin
                                bf <= !hwi;
                                km <= `TRUE;
`ifdef DEBUG
                                hist_capture <= `FALSE;
`endif
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_PCHWI;
                                state <= STORE1;
                        end
                `INT0,`INT1:
                        begin
                                pg2 <= `FALSE;
                                ir <= {8{`BRK}};
                                vect <= {vbr[31:9],ir[0],ir[15:8],2'b00};
                                state <= DECODE;
                        end
                `JMP:
                        begin
                                pc[15:0] <= ir[23:8];
                                state <= IFETCH;
                        end
                `JML:
                        begin
                                pc <= ir[39:8];
                                state <= IFETCH;
                        end
                `JMP_IND:
                        begin
                                radr <= ir[39:8];
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                        end
                `JMP_INDX:
                        begin
                                radr <= ir[39:8] + x;
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                        end
                `JMP_RIND:
                        begin
                                pc <= rfoa;
                                res <= pc + 32'd2;
                                Rt <= ir[15:12];
                                state <= IFETCH;
                        end
                `JSR:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                wdat <= pc+{31'd1,suppress_pcinc[0]};
                                pc <= {pc[31:16],ir[23:8]};
                                state <= STORE1;
                        end
                `JSR_RIND:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                wdat <= pc + 32'd2;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                pc <= rfoa;
                                state <= STORE1;
                        end
                `JSL,`JSR_INDX,`JSR_IND:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
                                pc <= ir[39:8];         // This pc assignment will be overridden later by JSR_INDX
                                state <= STORE1;
                        end
                `BSR:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                wdat <= pc+{31'd1,suppress_pcinc[0]};
                                pc <= pc + {{16{ir[23]}},ir[23:8]};
                                state <= STORE1;
                        end
                `RTS,`RTL:
                                begin
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                end
                `RTI:   begin
                                hist_capture <= `TRUE;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `SR_310;
                                state <= LOAD_MAC1;
                                end
                `BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA,
                `BGT,`BGE,`BLT,`BLE,`BHI,`BLS:
                        begin
                                if (ir[15:8]==8'h00) begin
                                        pg2 <= `FALSE;
                                        ir <= {8{`BRK}};
                                        pc <= pc;               // override the pc increment
                                        vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
                                        state <= DECODE;
                                end
                                else if (ir[15:8]==8'h1) begin
                                        if (takb)
                                                pc <= pc + {{16{ir[31]}},ir[31:16]};
                                        else
                                                pc <= pcp4;
                                end
                                else begin
                                        if (takb)
                                                pc <= pc + {{24{ir[15]}},ir[15:8]};
                                        else
                                                pc <= pcp2;
                                end
                        end
                `BRL:
                        begin
                                if (ir[23:8]==16'h0000) begin
                                        pg2 <= `FALSE;
                                        ir <= {8{`BRK}};
                                        vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
                                        pc <= pc;               // override the pc increment
                                        state <= DECODE;
                                end
                                else begin
                                        pc <= pc + {{16{ir[23]}},ir[23:8]};
                                        state <= IFETCH;
                                end
                        end
`ifdef SUPPORT_EXEC
                `EXEC,`ATNI:
                        begin
                                exbuf[31:0] <= rfoa;
                                exbuf[63:32] <= rfob;
                        end
`endif
                `PHP:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_SR;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PHA:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_ACC;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PHX:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_X;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PHY:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_Y;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PUSH:
                        begin
                                if (ir[15:12]==4'h0) begin
                                        radr <= isp_dec;
                                        wadr <= isp_dec;
                                        isp <= isp_dec;
                                end
                                else begin
                                        radr <= rfob-32'd1;
                                        wadr <= rfob-32'd1;
                                        wrrf <= 1'b1;
                                        Rt <= ir[15:12];
                                        res <= rfob-32'd1;
                                end
                                store_what <= `STW_A;
                                state <= STORE1;
                        end
                `PUSHA:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                ir[11:8] <= 4'd1;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                                isp <= isp_dec;
                        end
                `PLP:
                        begin
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `SR_310;
                                state <= LOAD_MAC1;
                        end
                `PLA:
                        begin
                                Rt <= 4'd1;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `PLX:
                        begin
                                Rt <= 4'd2;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `PLY:
                        begin
                                Rt <= 4'd3;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `POP:
                        begin
                                if (ir[11:8]!=4'h0) begin
                                        Rt <= ir[11:8];
                                        res <= rfoa+32'd1;
                                        wrrf <= 1'b1;
                                        radr <= rfoa;
                                end
                                else begin
                                        radr <= isp;
                                        isp <= isp_inc;
                                end
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `POPA:
                        begin
                                Rt <= 4'd15;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
`ifdef SUPPORT_STRING
                `MVN:
                        begin
                                Rt <= 4'd3;
                                radr <= x;
                                res <= x_inc;
                                load_what <= `WORD_312;
                                pc <= pc;
                                state <= LOAD_MAC1;
                        end
                `MVP:
                        begin
                                Rt <= 4'd3;
                                radr <= x;
                                res <= x_dec;
                                load_what <= `WORD_312;
                                pc <= pc;
                                state <= LOAD_MAC1;
                        end
                `STS:
                        begin
                                Rt <= 4'd3;
                                radr <= y;
                                wadr <= y;
                                store_what <= `STW_X;
                                acc <= acc_dec;
                                pc <= pc;
                                state <= STORE1;
                        end
                `CMPS:
                        begin
                                Rt <= 4'd3;
                                radr <= x;
                                res <= x_inc;
                                pc <= pc;
                                load_what <= `WORD_313;
                                state <= LOAD_MAC1;
                        end
`endif
                `PG2:   begin
                                        pg2 <= `TRUE;
                                        ir <= ir[63:8];
                                        state <= DECODE;
                                end
                default:        // unimplemented opcode
                        begin
                                res <= 32'd0;
                                pg2 <= `FALSE;
                                ir <= {8{`BRK}};
                                hwi <= `TRUE;
                                vect <= {vbr[31:9],9'd495,2'b00};
                                pc <= pc;               // override the pc increment
                                state <= DECODE;
                        end
                endcase
        end
endtask

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	32	robfinch	`task decode_tsk;`
24	20	robfinch	`begin`
25			first_ifetch <= `TRUE;
26			`Rt <= 4'h0; // Default`
27			`state <= IFETCH;`
28	30	robfinch	`pc <= pc + pc_inc;`
29	38	robfinch	`pc_inc2 <= pc_inc;`
30	30	robfinch	`a <= rfoa;`
31	32	robfinch	`res <= alu_out;`
32			`ttrig <= tf;`
33	35	robfinch	`oisp <= isp; // for bus retry`
34	30	robfinch	`// This case statement should include all opcodes or the opcode`
35			`// will end up being treated as an undefined operation.`
36	32	robfinch	`case(ir9)`
37	30	robfinch	`STP: clk_en <= 1'b0;
38			`NOP: ;
39			`// casex(ir[63:0])`
40			// {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp8;
41			// {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp7;
42			// {16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp6;
43			// {24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp5;
44			// {32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}: pc <= pcp4;
45			// {40'hxxxxxxxxxx,`NOP,`NOP,`NOP}: pc <= pcp3;
46			// {48'hxxxxxxxxxxxx,`NOP,`NOP}: pc <= pcp2;
47			// {56'hxxxxxxxxxxxxxx,`NOP}: pc <= pcp1;
48			`// endcase`
49			`CLC: cf <= 1'b0;
50			`SEC: cf <= 1'b1;
51			`CLV: vf <= 1'b0;
52			`CLI: im <= 1'b0;
53			`CLD: df <= 1'b0;
54			`SED: df <= 1'b1;
55			`SEI: im <= 1'b1;
56			`WAI: wai <= 1'b1;
57	32	robfinch	`TON: tf <= 1'b1;
58			`TOFF: tf <= 1'b0;
59			`HOFF: hist_capture <= 1'b0;
60	38	robfinch	`// Switching to 65c02 mode zeros out the upper part of the index registers.`
61			`// Switching to 65c816 mode does not zero out the upper part of the index registers,`
62			`// this is unlike switching from '02 to '816 mode. Also, the register size select`
63			`// bits are not affected.`
64			`XCE: begin
65			`em <= 1'b1;`
66			`m816 <= ~cf;`
67			`cf <= ~m816;`
68			`if (cf) begin`
69			`x[31:8] <= 24'd0;`
70			`y[31:8] <= 24'd0;`
71			`end`
72	32	robfinch	`ifdef SUPPORT_EM8
73	38	robfinch	`next_state(BYTE_IFETCH);`
74	32	robfinch	`endif
75			`end`
76			`DEX: Rt <= 4'd2;
77	25	robfinch	`// DEX/BNE accelerator`
78			// if (ir[15:8]==`BNE) begin
79			`// if (x!=32'd1) begin`
80			`// if (ir[23:16]==8'h01)`
81			`// pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1;`
82			`// else`
83			`// pc <= pc + {{24{ir[23]}},ir[23:16]} + 32'd1;`
84			`// end`
85			`// else begin`
86			`// if (ir[23:16]==8'h01)`
87			`// pc <= pcp5;`
88			`// else`
89			`// pc <= pcp3;`
90			`// end`
91			`// end`
92	32	robfinch	`INX: Rt <= 4'd2;
93			`DEY: Rt <= 4'd3;
94			`INY: Rt <= 4'd3;
95			`DEA: Rt <= 4'd1;
96			`INA: Rt <= 4'd1;
97			`TSX: Rt <= 4'd2;
98			`TSA: Rt <= 4'd1;
99			`TXS: ;
100			`TXA: Rt <= 4'd1;
101			`TXY: Rt <= 4'd3;
102			`TAX: Rt <= 4'd2;
103			`TAY: Rt <= 4'd3;
104			`TAS: ;
105			`TYA: Rt <= 4'd1;
106			`TYX: Rt <= 4'd2;
107			`TRS: ;
108	20	robfinch	`TSR: begin
109			`Rt <= ir[15:12];`
110			`case(ir[11:8])`
111	32	robfinch	`4'h0: ;`
112			`4'h2: ;`
113			`4'h3: ;`
114			`4'h4: ;`
115			`4'h5: lfsr <= {lfsr[30:0],lfsr_fb};`
116			`4'd7: ;`
117			`4'h8: ;`
118			`4'h9: ;`
119	35	robfinch	`ifdef DEBUG
120	32	robfinch	`4'hA: history_ndx <= history_ndx + 6'd1;`
121	35	robfinch	`endif
122	32	robfinch	`4'hE: ;`
123			`4'hF: ;`
124			`default: ;`
125	20	robfinch	`endcase`
126			`end`
127	32	robfinch	`ASL_ACC: Rt <= 4'd1;
128			`ROL_ACC: Rt <= 4'd1;
129			`LSR_ACC: Rt <= 4'd1;
130			`ROR_ACC: Rt <= 4'd1;
131	20	robfinch
132			`RR:
133			`begin`
134	30	robfinch	`Rt <= ir[19:16];`
135	20	robfinch	`case(ir[23:20])`
136	32	robfinch	`ADD_RR: b <= rfob;
137			`SUB_RR: b <= rfob;
138			`AND_RR: b <= rfob; // for bit flags
139			`OR_RR: b <= rfob;
140			`EOR_RR: b <= rfob;
141			`MUL_RR: begin b <= rfob; state <= MULDIV1; end
142			`MULS_RR: begin b <= rfob; state <= MULDIV1; end
143	30	robfinch	`ifdef SUPPORT_DIVMOD
144	32	robfinch	`DIV_RR: begin b <= rfob; state <= MULDIV1; end
145			`DIVS_RR: begin b <= rfob; state <= MULDIV1; end
146			`MOD_RR: begin b <= rfob; state <= MULDIV1; end
147			`MODS_RR: begin b <= rfob; state <= MULDIV1; end
148	30	robfinch	`endif
149			`ifdef SUPPORT_SHIFT
150			`ASL_RRR: begin b <= rfob; state <= CALC; end
151			`LSR_RRR: begin b <= rfob; state <= CALC; end
152			`endif
153			`default:`
154			`begin`
155			`Rt <= 4'h0;`
156	32	robfinch	pg2 <= `FALSE;
157	30	robfinch	ir <= {8{`BRK}};
158			hwi <= `TRUE;
159			`vect <= {vbr[31:9],9'd495,2'b00};`
160			`pc <= pc; // override the pc increment`
161			`state <= DECODE;`
162			`end`
163	20	robfinch	`endcase`
164			`end`
165	32	robfinch	`LD_RR: Rt <= ir[15:12];
166			`ASL_RR: Rt <= ir[15:12];
167			`ROL_RR: Rt <= ir[15:12];
168			`LSR_RR: Rt <= ir[15:12];
169			`ROR_RR: Rt <= ir[15:12];
170			`DEC_RR: Rt <= ir[15:12];
171			`INC_RR: Rt <= ir[15:12];
172	38	robfinch	`/*`
173			`Can't P&R this`
174			`ADD_R: begin Rt <= ir[11: 8]; b <= rfob; end
175			`SUB_R: begin Rt <= ir[11: 8]; b <= rfob; end
176			`OR_R: begin Rt <= ir[11: 8]; b <= rfob; end
177			`AND_R: begin Rt <= ir[11: 8]; b <= rfob; end
178			`EOR_R: begin Rt <= ir[11: 8]; b <= rfob; end
179			`*/`
180			`ADD_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
181			`SUB_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
182			`OR_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
183			`AND_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
184			`EOR_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
185	20	robfinch
186	32	robfinch	`ADD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
187			`SUB_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
188			`MUL_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
189			`ifdef SUPPORT_DIVMOD
190			`DIV_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
191			`MOD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
192			`endif
193			`OR_IMM8: begin Rt <= ir[15:12]; end
194			`AND_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
195			`EOR_IMM8: begin Rt <= ir[15:12]; end
196			`CMP_IMM8: ;
197	30	robfinch	`ifdef SUPPORT_SHIFT
198	32	robfinch	`ASL_IMM8: begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
199			`LSR_IMM8: begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
200	30	robfinch	`endif
201	32	robfinch
202			`ADD_IMM16: begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
203			`SUB_IMM16: begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
204			`MUL_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
205			`ifdef SUPPORT_DIVMOD
206			`DIV_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
207			`MOD_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
208			`endif
209			`OR_IMM16: begin Rt <= ir[15:12]; end
210			`AND_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
211			`EOR_IMM16: begin Rt <= ir[15:12]; end
212	20	robfinch
213	32	robfinch	`ADD_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
214			`SUB_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
215			`MUL_IMM16: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
216			`ifdef SUPPORT_DIVMOD
217			`DIV_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
218			`MOD_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
219			`endif
220			`OR_IMM32: begin Rt <= ir[15:12]; end
221			`AND_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
222			`EOR_IMM32: begin Rt <= ir[15:12]; end
223	20	robfinch
224	32	robfinch	`LDA_IMM32: Rt <= 4'd1;
225			`LDX_IMM32: Rt <= 4'd2;
226			`LDY_IMM32: Rt <= 4'd3;
227			`LDA_IMM16: Rt <= 4'd1;
228			`LDX_IMM16: Rt <= 4'd2;
229			`LDA_IMM8: Rt <= 4'd1;
230			`LDX_IMM8: Rt <= 4'd2;
231	20	robfinch
232	32	robfinch	`SUB_SP8: ;
233			`SUB_SP16: ;
234			`SUB_SP32: ;
235	23	robfinch
236	32	robfinch	`CPX_IMM32: ;
237			`CPY_IMM32: ;
238	30	robfinch
239	32	robfinch	`LDX_ZPX:
240	20	robfinch	`begin`
241	32	robfinch	`Rt <= 4'd2;`
242	20	robfinch	`radr <= zpx32xy_address;`
243	21	robfinch	load_what <= `WORD_311;
244			`state <= LOAD_MAC1;`
245	20	robfinch	`end`
246	32	robfinch	`LDY_ZPX:
247			`begin`
248			`Rt <= 4'd3;`
249			`radr <= zpx32xy_address;`
250			load_what <= `WORD_311;
251			`state <= LOAD_MAC1;`
252			`end`
253	20	robfinch	`ORB_ZPX:
254			`begin`
255			`Rt <= ir[19:16];`
256			`radr <= zpx32_address[31:2];`
257			`radr2LSB <= zpx32_address[1:0];`
258	21	robfinch	load_what <= `WORD_310;
259			`state <= LOAD_MAC1;`
260	20	robfinch	`end`
261	32	robfinch	`LDX_ABS:
262	20	robfinch	`begin`
263	32	robfinch	`Rt <= 4'd2;`
264	20	robfinch	`radr <= ir[39:8];`
265	21	robfinch	load_what <= `WORD_311;
266			`state <= LOAD_MAC1;`
267	20	robfinch	`end`
268	32	robfinch	`LDY_ABS:
269			`begin`
270			`Rt <= 4'd3;`
271			`radr <= ir[39:8];`
272			load_what <= `WORD_311;
273			`state <= LOAD_MAC1;`
274			`end`
275	20	robfinch	`ORB_ABS:
276			`begin`
277			`Rt <= ir[15:12];`
278			`radr <= ir[47:18];`
279			`radr2LSB <= ir[17:16];`
280	21	robfinch	load_what <= `WORD_310;
281			`state <= LOAD_MAC1;`
282	20	robfinch	`end`
283	32	robfinch	`LDX_ABSY:
284	20	robfinch	`begin`
285	32	robfinch	`Rt <= 4'd2;`
286	20	robfinch	`radr <= absx32xy_address;`
287	21	robfinch	load_what <= `WORD_311;
288			`state <= LOAD_MAC1;`
289	20	robfinch	`end`
290	32	robfinch	`LDY_ABSX:
291			`begin`
292			`Rt <= 4'd3;`
293			`radr <= absx32xy_address;`
294			load_what <= `WORD_311;
295			`state <= LOAD_MAC1;`
296			`end`
297	20	robfinch	`ORB_ABSX:
298			`begin`
299			`Rt <= ir[19:16];`
300			`radr <= absx32_address[31:2];`
301			`radr2LSB <= absx32_address[1:0];`
302	21	robfinch	load_what <= `WORD_310;
303			`state <= LOAD_MAC1;`
304	20	robfinch	`end`
305			`ST_ZPX:
306			`begin`
307			`wadr <= zpx32_address;`
308	30	robfinch	store_what <= `STW_RFA;
309	20	robfinch	`state <= STORE1;`
310			`end`
311			`STB_ZPX:
312			`begin`
313			`wadr <= zpx32_address[31:2];`
314			`wadr2LSB <= zpx32_address[1:0];`
315	30	robfinch	store_what <= `STW_RFA8;
316	20	robfinch	`state <= STORE1;`
317			`end`
318	23	robfinch	`ST_DSP:
319			`begin`
320	38	robfinch	`wadr <= {24'b0,ir[23:16]} + isp;`
321	30	robfinch	store_what <= `STW_RFA;
322	23	robfinch	`state <= STORE1;`
323			`end`
324	20	robfinch	`ST_ABS:
325			`begin`
326			`wadr <= ir[47:16];`
327	30	robfinch	store_what <= `STW_RFA;
328	20	robfinch	`state <= STORE1;`
329			`end`
330			`STB_ABS:
331			`begin`
332			`wadr <= ir[47:18];`
333			`wadr2LSB <= ir[17:16];`
334	30	robfinch	store_what <= `STW_RFA8;
335	20	robfinch	`state <= STORE1;`
336			`end`
337			`ST_ABSX:
338			`begin`
339			`wadr <= absx32_address;`
340	30	robfinch	store_what <= `STW_RFA;
341	20	robfinch	`state <= STORE1;`
342			`end`
343			`STB_ABSX:
344			`begin`
345			`wadr <= absx32_address[31:2];`
346			`wadr2LSB <= absx32_address[1:0];`
347	30	robfinch	store_what <= `STW_RFA8;
348	20	robfinch	`state <= STORE1;`
349			`end`
350			`STX_ZPX:
351			`begin`
352	30	robfinch	`wadr <= zpx32xy_address;`
353			store_what <= `STW_X;
354	20	robfinch	`state <= STORE1;`
355			`end`
356			`STX_ABS:
357			`begin`
358			`wadr <= ir[39:8];`
359	30	robfinch	store_what <= `STW_X;
360	20	robfinch	`state <= STORE1;`
361			`end`
362			`STY_ZPX:
363			`begin`
364	30	robfinch	`wadr <= zpx32xy_address;`
365			store_what <= `STW_Y;
366	20	robfinch	`state <= STORE1;`
367			`end`
368			`STY_ABS:
369			`begin`
370			`wadr <= ir[39:8];`
371	30	robfinch	store_what <= `STW_Y;
372	20	robfinch	`state <= STORE1;`
373			`end`
374	36	robfinch	`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`TRB_ZPX:
375	20	robfinch	`begin`
376			`Rt <= ir[19:16];`
377			`radr <= zpx32_address;`
378	21	robfinch	load_what <= `WORD_310;
379			`state <= LOAD_MAC1;`
380	20	robfinch	`end`
381	36	robfinch	`LEA_ZPX:
382			`begin`
383			`Rt <= ir[19:16];`
384			`res <= zpx32_address;`
385			`state <= IFETCH;`
386			`end`
387	32	robfinch	`// Trim a clock cycle off of loads by testing for Ra = 0.`
388	36	robfinch	`OR_ZPX,`EOR_ZPX,`TSB_ZPX:
389	32	robfinch	`begin`
390			`Rt <= ir[19:16];`
391			`radr <= zpx32_address;`
392			load_what <= (Ra==4'd0) ? `WORD_311: `WORD_310;
393			`state <= LOAD_MAC1;`
394			`end`
395	20	robfinch	`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
396			`begin`
397	30	robfinch	`radr <= zpx32xy_address;`
398	21	robfinch	load_what <= `WORD_310;
399			`state <= LOAD_MAC1;`
400	20	robfinch	`end`
401	32	robfinch	`BMS_ZPX,`BMC_ZPX,`BMF_ZPX,`BMT_ZPX:
402			`begin`
403			`radr <= zpx32xy_address + acc[31:5];`
404			load_what <= `WORD_310;
405			`state <= LOAD_MAC1;`
406			`end`
407	36	robfinch	`LEA_DSP:
408			`begin`
409			`Rt <= ir[15:12];`
410	38	robfinch	`res <= {24'b0,ir[23:16]} + isp;`
411	36	robfinch	`state <= IFETCH;`
412			`end`
413	23	robfinch	`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
414			`begin`
415			`Rt <= ir[15:12];`
416	38	robfinch	`radr <= {24'b0,ir[23:16]} + isp;`
417	23	robfinch	load_what <= `WORD_310;
418			`state <= LOAD_MAC1;`
419			`end`
420	36	robfinch	`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX,`LEA_IX:
421	20	robfinch	`begin`
422	25	robfinch	if (ir[7:0]!=`ST_IX) // for ST_IX, Rt=0
423	20	robfinch	`Rt <= ir[19:16];`
424	30	robfinch	`radr <= zpx32_address;`
425	21	robfinch	load_what <= `IA_310;
426	30	robfinch	store_what <= `STW_A;
427	21	robfinch	`state <= LOAD_MAC1;`
428	20	robfinch	`end`
429	36	robfinch	`LEA_RIND:
430			`begin`
431			`Rt <= ir[19:16];`
432			`res <= rfob;`
433			`state <= IFETCH;`
434			`end`
435	25	robfinch	`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
436	20	robfinch	`begin`
437			`radr <= rfob;`
438	25	robfinch	`Rt <= ir[19:16];`
439			load_what <= `WORD_310;
440			`state <= LOAD_MAC1;`
441	20	robfinch	`end`
442	25	robfinch	`ST_RIND:
443			`begin`
444			`wadr <= rfob;`
445	30	robfinch	store_what <= `STW_RFA;
446	25	robfinch	`state <= STORE1;`
447			`end`
448	36	robfinch	`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY,`LEA_IY:
449	20	robfinch	`begin`
450	25	robfinch	if (ir[7:0]!=`ST_IY) // for ST_IY, Rt=0
451	20	robfinch	`Rt <= ir[19:16];`
452	21	robfinch	`isIY <= 1'b1;`
453	30	robfinch	`radr <= ir[31:20];`
454	21	robfinch	load_what <= `IA_310;
455	30	robfinch	store_what <= `STW_A;
456	21	robfinch	`state <= LOAD_MAC1;`
457	20	robfinch	`end`
458	36	robfinch	`LEA_ABS:
459	20	robfinch	`begin`
460	36	robfinch	`res <= ir[47:16];`
461			`Rt <= ir[15:12];`
462			`state <= IFETCH;`
463			`end`
464			`OR_ABS,`EOR_ABS,`TSB_ABS:
465			`begin`
466	20	robfinch	`radr <= ir[47:16];`
467			`Rt <= ir[15:12];`
468	32	robfinch	load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
469			`state <= LOAD_MAC1;`
470			`end`
471	36	robfinch	`ADD_ABS,`SUB_ABS,`AND_ABS,`TRB_ABS:
472	32	robfinch	`begin`
473			`radr <= ir[47:16];`
474			`Rt <= ir[15:12];`
475	21	robfinch	load_what <= `WORD_310;
476			`state <= LOAD_MAC1;`
477	20	robfinch	`end`
478			`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
479			`begin`
480			`radr <= ir[39:8];`
481	21	robfinch	load_what <= `WORD_310;
482			`state <= LOAD_MAC1;`
483	20	robfinch	`end`
484	38	robfinch	`SPL_ABS:
485			`begin`
486			`Rt <= 4'h0;`
487			`radr <= ir[39:8];`
488			load_what <= `WORD_310;
489			`state <= LOAD_MAC1;`
490			`end`
491	32	robfinch	`BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS:
492	20	robfinch	`begin`
493	32	robfinch	`radr <= ir[39:8] + acc[31:5];`
494			load_what <= `WORD_310;
495			`state <= LOAD_MAC1;`
496			`end`
497	36	robfinch	`LEA_ABSX:
498			`begin`
499			`res <= absx32_address;`
500			`Rt <= ir[19:16];`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [decode.v] - Blame information for rev 38