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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
task decode_tsk;
        begin
                first_ifetch <= `TRUE;
                Rt <= 4'h0;             // Default
                state <= IFETCH;
                pc <= pc + pc_inc;
                a <= rfoa;
                res <= alu_out;
                ttrig <= tf;
                oisp <= isp;    // for bus retry
                // This case statement should include all opcodes or the opcode
                // will end up being treated as an undefined operation.
                case(ir9)
                `STP:   clk_en <= 1'b0;
                `NOP:   ;
//                              casex(ir[63:0])
//                              {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}:      pc <= pcp8;
//                              {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}:     pc <= pcp7;
//                              {16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}:       pc <= pcp6;
//                              {24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}:  pc <= pcp5;
//                              {32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}:     pc <= pcp4;
//                              {40'hxxxxxxxxxx,`NOP,`NOP,`NOP}:        pc <= pcp3;
//                              {48'hxxxxxxxxxxxx,`NOP,`NOP}:   pc <= pcp2;
//                              {56'hxxxxxxxxxxxxxx,`NOP}:      pc <= pcp1;
//                              endcase
                `CLC:   cf <= 1'b0;
                `SEC:   cf <= 1'b1;
                `CLV:   vf <= 1'b0;
                `CLI:   im <= 1'b0;
                `CLD:   df <= 1'b0;
                `SED:   df <= 1'b1;
                `SEI:   im <= 1'b1;
                `WAI:   wai <= 1'b1;
                `TON:   tf <= 1'b1;
                `TOFF:  tf <= 1'b0;
                `HOFF:  hist_capture <= 1'b0;
                `EMM:   begin em <= 1'b1;
`ifdef SUPPORT_EM8
                                state <= BYTE_IFETCH;
`endif
                                end
                `DEX:   Rt <= 4'd2;
                                        // DEX/BNE accelerator
//                                      if (ir[15:8]==`BNE) begin
//                                              if (x!=32'd1) begin
//                                                      if (ir[23:16]==8'h01)
//                                                              pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1;
//                                                      else
//                                                              pc <= pc + {{24{ir[23]}},ir[23:16]} + 32'd1;
//                                              end
//                                              else begin
//                                                      if (ir[23:16]==8'h01)
//                                                              pc <= pcp5;
//                                                      else
//                                                              pc <= pcp3;
//                                              end
//                                      end
                `INX:   Rt <= 4'd2;
                `DEY:   Rt <= 4'd3;
                `INY:   Rt <= 4'd3;
                `DEA:   Rt <= 4'd1;
                `INA:   Rt <= 4'd1;
                `TSX:   Rt <= 4'd2;
                `TSA:   Rt <= 4'd1;
                `TXS:   ;
                `TXA:   Rt <= 4'd1;
                `TXY:   Rt <= 4'd3;
                `TAX:   Rt <= 4'd2;
                `TAY:   Rt <= 4'd3;
                `TAS:   ;
                `TYA:   Rt <= 4'd1;
                `TYX:   Rt <= 4'd2;
                `TRS:           ;
                `TSR:           begin
                                                Rt <= ir[15:12];
                                                case(ir[11:8])
                                                4'h0:   ;
                                                4'h2:   ;
                                                4'h3:   ;
                                                4'h4:   ;
                                                4'h5:   lfsr <= {lfsr[30:0],lfsr_fb};
                                                4'd7:   ;
                                                4'h8:   ;
                                                4'h9:   ;
`ifdef DEBUG
                                                4'hA:   history_ndx <= history_ndx + 6'd1;
`endif
                                                4'hE:   ;
                                                4'hF:   ;
                                                default:        ;
                                                endcase
                                        end
                `ASL_ACC:       Rt <= 4'd1;
                `ROL_ACC:       Rt <= 4'd1;
                `LSR_ACC:       Rt <= 4'd1;
                `ROR_ACC:       Rt <= 4'd1;
 
                `RR:
                        begin
                                Rt <= ir[19:16];
                                case(ir[23:20])
                                `ADD_RR:        b <= rfob;
                                `SUB_RR:        b <= rfob;
                                `AND_RR:        b <= rfob;      // for bit flags
                                `OR_RR:         b <= rfob;
                                `EOR_RR:        b <= rfob;
                                `MUL_RR:        begin b <= rfob; state <= MULDIV1; end
                                `MULS_RR:       begin b <= rfob; state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                                `DIV_RR:        begin b <= rfob; state <= MULDIV1; end
                                `DIVS_RR:       begin b <= rfob; state <= MULDIV1; end
                                `MOD_RR:        begin b <= rfob; state <= MULDIV1; end
                                `MODS_RR:       begin b <= rfob; state <= MULDIV1; end
`endif
`ifdef SUPPORT_SHIFT
                                `ASL_RRR:       begin b <= rfob; state <= CALC; end
                                `LSR_RRR:       begin b <= rfob; state <= CALC; end
`endif
                                default:
                                        begin
                                                Rt <= 4'h0;
                                                pg2 <= `FALSE;
                                                ir <= {8{`BRK}};
                                                hwi <= `TRUE;
                                                vect <= {vbr[31:9],9'd495,2'b00};
                                                pc <= pc;               // override the pc increment
                                                state <= DECODE;
                                        end
                                endcase
                        end
                `LD_RR:         Rt <= ir[15:12];
                `ASL_RR:        Rt <= ir[15:12];
                `ROL_RR:        Rt <= ir[15:12];
                `LSR_RR:        Rt <= ir[15:12];
                `ROR_RR:        Rt <= ir[15:12];
                `DEC_RR:        Rt <= ir[15:12];
                `INC_RR:        Rt <= ir[15:12];
 
                `ADD_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
                `SUB_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
                `MUL_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                `DIV_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
                `MOD_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
`endif
                `OR_IMM8:       begin Rt <= ir[15:12]; end
                `AND_IMM8:      begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
                `EOR_IMM8:      begin Rt <= ir[15:12]; end
                `CMP_IMM8:      ;
`ifdef SUPPORT_SHIFT
                `ASL_IMM8:      begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
                `LSR_IMM8:      begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
`endif
 
                `ADD_IMM16:     begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
                `SUB_IMM16:     begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
                `MUL_IMM16:     begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                `DIV_IMM16:     begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
                `MOD_IMM16:     begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
`endif
                `OR_IMM16:      begin Rt <= ir[15:12]; end
                `AND_IMM16:     begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
                `EOR_IMM16:     begin Rt <= ir[15:12]; end
 
                `ADD_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; end
                `SUB_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; end
                `MUL_IMM16:     begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
`ifdef SUPPORT_DIVMOD
                `DIV_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
                `MOD_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
`endif
                `OR_IMM32:      begin Rt <= ir[15:12]; end
                `AND_IMM32:     begin Rt <= ir[15:12]; b <= ir[47:16]; end
                `EOR_IMM32:     begin Rt <= ir[15:12]; end
 
                `LDA_IMM32:     Rt <= 4'd1;
                `LDX_IMM32:     Rt <= 4'd2;
                `LDY_IMM32: Rt <= 4'd3;
                `LDA_IMM16:     Rt <= 4'd1;
                `LDX_IMM16: Rt <= 4'd2;
                `LDA_IMM8: Rt <= 4'd1;
                `LDX_IMM8: Rt <= 4'd2;
 
                `SUB_SP8:       ;
                `SUB_SP16:      ;
                `SUB_SP32:      ;
 
                `CPX_IMM32:     ;
                `CPY_IMM32:     ;
 
                `LDX_ZPX:
                        begin
                                Rt <= 4'd2;
                                radr <= zpx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `LDY_ZPX:
                        begin
                                Rt <= 4'd3;
                                radr <= zpx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `ORB_ZPX:
                        begin
                                Rt <= ir[19:16];
                                radr <= zpx32_address[31:2];
                                radr2LSB <= zpx32_address[1:0];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LDX_ABS:
                        begin
                                Rt <= 4'd2;
                                radr <= ir[39:8];
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `LDY_ABS:
                        begin
                                Rt <= 4'd3;
                                radr <= ir[39:8];
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `ORB_ABS:
                        begin
                                Rt <= ir[15:12];
                                radr <= ir[47:18];
                                radr2LSB <= ir[17:16];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LDX_ABSY:
                        begin
                                Rt <= 4'd2;
                                radr <= absx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `LDY_ABSX:
                        begin
                                Rt <= 4'd3;
                                radr <= absx32xy_address;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `ORB_ABSX:
                        begin
                                Rt <= ir[19:16];
                                radr <= absx32_address[31:2];
                                radr2LSB <= absx32_address[1:0];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ST_ZPX:
                        begin
                                wadr <= zpx32_address;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `STB_ZPX:
                        begin
                                wadr <= zpx32_address[31:2];
                                wadr2LSB <= zpx32_address[1:0];
                                store_what <= `STW_RFA8;
                                state <= STORE1;
                        end
                `ST_DSP:
                        begin
                                wadr <= {{24{ir[23]}},ir[23:16]} + isp;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `ST_ABS:
                        begin
                                wadr <= ir[47:16];
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `STB_ABS:
                        begin
                                wadr <= ir[47:18];
                                wadr2LSB <= ir[17:16];
                                store_what <= `STW_RFA8;
                                state <= STORE1;
                        end
                `ST_ABSX:
                        begin
                                wadr <= absx32_address;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `STB_ABSX:
                        begin
                                wadr <= absx32_address[31:2];
                                wadr2LSB <= absx32_address[1:0];
                                store_what <= `STW_RFA8;
                                state <= STORE1;
                        end
                `STX_ZPX:
                        begin
                                wadr <= zpx32xy_address;
                                store_what <= `STW_X;
                                state <= STORE1;
                        end
                `STX_ABS:
                        begin
                                wadr <= ir[39:8];
                                store_what <= `STW_X;
                                state <= STORE1;
                        end
                `STY_ZPX:
                        begin
                                wadr <= zpx32xy_address;
                                store_what <= `STW_Y;
                                state <= STORE1;
                        end
                `STY_ABS:
                        begin
                                wadr <= ir[39:8];
                                store_what <= `STW_Y;
                                state <= STORE1;
                        end
                `ADD_ZPX,`SUB_ZPX,`AND_ZPX,`TRB_ZPX:
                        begin
                                Rt <= ir[19:16];
                                radr <= zpx32_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LEA_ZPX:
                        begin
                                Rt <= ir[19:16];
                                res <= zpx32_address;
                                state <= IFETCH;
                        end
                // Trim a clock cycle off of loads by testing for Ra = 0.
                `OR_ZPX,`EOR_ZPX,`TSB_ZPX:
                        begin
                                Rt <= ir[19:16];
                                radr <= zpx32_address;
                                load_what <= (Ra==4'd0) ? `WORD_311: `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BMS_ZPX,`BMC_ZPX,`BMF_ZPX,`BMT_ZPX:
                        begin
                                radr <= zpx32xy_address + acc[31:5];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LEA_DSP:
                        begin
                                Rt <= ir[15:12];
                                res <= {{24{ir[23]}},ir[23:16]} + isp;
                                state <= IFETCH;
                        end
                `ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
                        begin
                                Rt <= ir[15:12];
                                radr <= {{24{ir[23]}},ir[23:16]} + isp;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX,`LEA_IX:
                        begin
                                if (ir[7:0]!=`ST_IX)     // for ST_IX, Rt=0
                                        Rt <= ir[19:16];
                                radr <= zpx32_address;
                                load_what <= `IA_310;
                                store_what <= `STW_A;
                                state <= LOAD_MAC1;
                        end
                `LEA_RIND:
                        begin
                                Rt <= ir[19:16];
                                res <= rfob;
                                state <= IFETCH;
                        end
                `ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
                        begin
                                radr <= rfob;
                                Rt <= ir[19:16];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ST_RIND:
                        begin
                                wadr <= rfob;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                        end
                `ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY,`LEA_IY:
                        begin
                                if (ir[7:0]!=`ST_IY)     // for ST_IY, Rt=0
                                        Rt <= ir[19:16];
                                isIY <= 1'b1;
                                radr <= ir[31:20];
                                load_what <= `IA_310;
                                store_what <= `STW_A;
                                state <= LOAD_MAC1;
                        end
                `LEA_ABS:
                        begin
                                res <= ir[47:16];
                                Rt <= ir[15:12];
                                state <= IFETCH;
                        end
                `OR_ABS,`EOR_ABS,`TSB_ABS:
                        begin
                                radr <= ir[47:16];
                                Rt <= ir[15:12];
                                load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ADD_ABS,`SUB_ABS,`AND_ABS,`TRB_ABS:
                        begin
                                radr <= ir[47:16];
                                Rt <= ir[15:12];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS:
                        begin
                                radr <= ir[39:8] + acc[31:5];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `LEA_ABSX:
                        begin
                                res <= absx32_address;
                                Rt <= ir[19:16];
                                state <= IFETCH;
                        end
                `ADD_ABSX,`SUB_ABSX,`AND_ABSX:
                        begin
                                radr <= absx32_address;
                                Rt <= ir[19:16];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `OR_ABSX,`EOR_ABSX:
                        begin
                                radr <= absx32_address;
                                Rt <= ir[19:16];
                                load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
                        begin
                                radr <= absx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BMS_ABSX,`BMC_ABSX,`BMF_ABSX,`BMT_ABSX:
                        begin
                                radr <= absx32xy_address + acc[31:5];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
 
                `CPX_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `CPY_ZPX:
                        begin
                                radr <= zpx32xy_address;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `CPX_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `CPY_ABS:
                        begin
                                radr <= ir[39:8];
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                        end
                `BRK:
                        begin
                                bf <= !hwi;
                                km <= `TRUE;
`ifdef DEBUG
                                hist_capture <= `FALSE;
`endif
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_PCHWI;
                                state <= STORE1;
                        end
                `INT0,`INT1:
                        begin
                                pg2 <= `FALSE;
                                ir <= {8{`BRK}};
                                vect <= {vbr[31:9],ir[15:7],2'b00};
                                state <= DECODE;
                        end
                `JMP:
                        begin
                                pc[15:0] <= ir[23:8];
                                state <= IFETCH;
                        end
                `JML:
                        begin
                                pc <= ir[39:8];
                                state <= IFETCH;
                        end
                `JMP_IND:
                        begin
                                radr <= ir[39:8];
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                        end
                `JMP_INDX:
                        begin
                                radr <= ir[39:8] + x;
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                        end
                `JMP_RIND:
                        begin
                                pc <= rfoa;
                                res <= pc + 32'd2;
                                Rt <= ir[15:12];
                                state <= IFETCH;
                        end
                `JSR:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                wdat <= pc+{31'd1,suppress_pcinc[0]};
                                pc <= {pc[31:16],ir[23:8]};
                                state <= STORE1;
                        end
                `JSR_RIND:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                wdat <= pc + 32'd2;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                pc <= rfoa;
                                state <= STORE1;
                        end
                `JSL,`JSR_INDX,`JSR_IND:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
                                pc <= ir[39:8];         // This pc assignment will be overridden later by JSR_INDX
                                state <= STORE1;
                        end
                `BSR:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_DEF;
                                wdat <= pc+{31'd1,suppress_pcinc[0]};
                                pc <= pc + {{16{ir[23]}},ir[23:8]};
                                state <= STORE1;
                        end
                `RTS,`RTL:
                                begin
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                end
                `RTI:   begin
                                hist_capture <= `TRUE;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `SR_310;
                                state <= LOAD_MAC1;
                                end
                `BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA,
                `BGT,`BGE,`BLT,`BLE,`BHI,`BLS:
                        begin
                                if (ir[15:8]==8'h00) begin
                                        pg2 <= `FALSE;
                                        ir <= {8{`BRK}};
                                        pc <= pc;               // override the pc increment
                                        vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
                                        state <= DECODE;
                                end
                                else if (ir[15:8]==8'h1) begin
                                        if (takb)
                                                pc <= pc + {{16{ir[31]}},ir[31:16]};
                                        else
                                                pc <= pcp4;
                                end
                                else begin
                                        if (takb)
                                                pc <= pc + {{24{ir[15]}},ir[15:8]};
                                        else
                                                pc <= pcp2;
                                end
                        end
                `BRL:
                        begin
                                if (ir[23:8]==16'h0000) begin
                                        pg2 <= `FALSE;
                                        ir <= {8{`BRK}};
                                        vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
                                        pc <= pc;               // override the pc increment
                                        state <= DECODE;
                                end
                                else begin
                                        pc <= pc + {{16{ir[23]}},ir[23:8]};
                                        state <= IFETCH;
                                end
                        end
`ifdef SUPPORT_EXEC
                `EXEC,`ATNI:
                        begin
                                exbuf[31:0] <= rfoa;
                                exbuf[63:32] <= rfob;
                        end
`endif
                `PHP:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_SR;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PHA:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_ACC;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PHX:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_X;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PHY:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                store_what <= `STW_Y;
                                isp <= isp_dec;
                                state <= STORE1;
                        end
                `PUSH:
                        begin
                                if (ir[15:12]==4'h0) begin
                                        radr <= isp_dec;
                                        wadr <= isp_dec;
                                        isp <= isp_dec;
                                end
                                else begin
                                        radr <= rfob-32'd1;
                                        wadr <= rfob-32'd1;
                                        wrrf <= 1'b1;
                                        Rt <= ir[15:12];
                                        res <= rfob-32'd1;
                                end
                                store_what <= `STW_A;
                                state <= STORE1;
                        end
                `PUSHA:
                        begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                ir[11:8] <= 4'd1;
                                store_what <= `STW_RFA;
                                state <= STORE1;
                                isp <= isp_dec;
                        end
                `PLP:
                        begin
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `SR_310;
                                state <= LOAD_MAC1;
                        end
                `PLA:
                        begin
                                Rt <= 4'd1;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `PLX:
                        begin
                                Rt <= 4'd2;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `PLY:
                        begin
                                Rt <= 4'd3;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `POP:
                        begin
                                if (ir[11:8]!=4'h0) begin
                                        Rt <= ir[11:8];
                                        res <= rfoa+32'd1;
                                        wrrf <= 1'b1;
                                        radr <= rfoa;
                                end
                                else begin
                                        radr <= isp;
                                        isp <= isp_inc;
                                end
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
                `POPA:
                        begin
                                Rt <= 4'd15;
                                radr <= isp;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                        end
`ifdef SUPPORT_STRING
                `MVN:
                        begin
                                Rt <= 4'd3;
                                radr <= x;
                                res <= x + 32'd1;
                                load_what <= `WORD_312;
                                state <= LOAD_MAC1;
                        end
                `MVP:
                        begin
                                Rt <= 4'd3;
                                radr <= x;
                                res <= x - 32'd1;
                                load_what <= `WORD_312;
                                state <= LOAD_MAC1;
                        end
                `STS:
                        begin
                                Rt <= 4'd3;
                                radr <= y;
                                wadr <= y;
                                store_what <= `STW_X;
                                acc <= acc - 32'd1;
                                state <= STORE1;
                        end
                `CMPS:
                        begin
                                Rt <= 4'd3;
                                radr <= x;
                                res <= x + 32'd1;
                                load_what <= `WORD_313;
                                state <= LOAD_MAC1;
                        end
`endif
                `PG2:   begin
                                        pg2 <= `TRUE;
                                        ir <= ir[63:8];
                                        state <= DECODE;
                                end
                default:        // unimplemented opcode
                        begin
                                res <= 32'd0;
                                pg2 <= `FALSE;
                                ir <= {8{`BRK}};
                                hwi <= `TRUE;
                                vect <= {vbr[31:9],9'd495,2'b00};
                                pc <= pc;               // override the pc increment
                                state <= DECODE;
                        end
                endcase
        end
endtask

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	32	robfinch	`task decode_tsk;`
24	20	robfinch	`begin`
25			first_ifetch <= `TRUE;
26			`Rt <= 4'h0; // Default`
27			`state <= IFETCH;`
28	30	robfinch	`pc <= pc + pc_inc;`
29			`a <= rfoa;`
30	32	robfinch	`res <= alu_out;`
31			`ttrig <= tf;`
32	35	robfinch	`oisp <= isp; // for bus retry`
33	30	robfinch	`// This case statement should include all opcodes or the opcode`
34			`// will end up being treated as an undefined operation.`
35	32	robfinch	`case(ir9)`
36	30	robfinch	`STP: clk_en <= 1'b0;
37			`NOP: ;
38			`// casex(ir[63:0])`
39			// {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp8;
40			// {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp7;
41			// {16'hxxxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp6;
42			// {24'hxxxxxx,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp5;
43			// {32'hxxxxxxxx,`NOP,`NOP,`NOP,`NOP}: pc <= pcp4;
44			// {40'hxxxxxxxxxx,`NOP,`NOP,`NOP}: pc <= pcp3;
45			// {48'hxxxxxxxxxxxx,`NOP,`NOP}: pc <= pcp2;
46			// {56'hxxxxxxxxxxxxxx,`NOP}: pc <= pcp1;
47			`// endcase`
48			`CLC: cf <= 1'b0;
49			`SEC: cf <= 1'b1;
50			`CLV: vf <= 1'b0;
51			`CLI: im <= 1'b0;
52			`CLD: df <= 1'b0;
53			`SED: df <= 1'b1;
54			`SEI: im <= 1'b1;
55			`WAI: wai <= 1'b1;
56	32	robfinch	`TON: tf <= 1'b1;
57			`TOFF: tf <= 1'b0;
58			`HOFF: hist_capture <= 1'b0;
59			`EMM: begin em <= 1'b1;
60			`ifdef SUPPORT_EM8
61			`state <= BYTE_IFETCH;`
62			`endif
63			`end`
64			`DEX: Rt <= 4'd2;
65	25	robfinch	`// DEX/BNE accelerator`
66			// if (ir[15:8]==`BNE) begin
67			`// if (x!=32'd1) begin`
68			`// if (ir[23:16]==8'h01)`
69			`// pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1;`
70			`// else`
71			`// pc <= pc + {{24{ir[23]}},ir[23:16]} + 32'd1;`
72			`// end`
73			`// else begin`
74			`// if (ir[23:16]==8'h01)`
75			`// pc <= pcp5;`
76			`// else`
77			`// pc <= pcp3;`
78			`// end`
79			`// end`
80	32	robfinch	`INX: Rt <= 4'd2;
81			`DEY: Rt <= 4'd3;
82			`INY: Rt <= 4'd3;
83			`DEA: Rt <= 4'd1;
84			`INA: Rt <= 4'd1;
85			`TSX: Rt <= 4'd2;
86			`TSA: Rt <= 4'd1;
87			`TXS: ;
88			`TXA: Rt <= 4'd1;
89			`TXY: Rt <= 4'd3;
90			`TAX: Rt <= 4'd2;
91			`TAY: Rt <= 4'd3;
92			`TAS: ;
93			`TYA: Rt <= 4'd1;
94			`TYX: Rt <= 4'd2;
95			`TRS: ;
96	20	robfinch	`TSR: begin
97			`Rt <= ir[15:12];`
98			`case(ir[11:8])`
99	32	robfinch	`4'h0: ;`
100			`4'h2: ;`
101			`4'h3: ;`
102			`4'h4: ;`
103			`4'h5: lfsr <= {lfsr[30:0],lfsr_fb};`
104			`4'd7: ;`
105			`4'h8: ;`
106			`4'h9: ;`
107	35	robfinch	`ifdef DEBUG
108	32	robfinch	`4'hA: history_ndx <= history_ndx + 6'd1;`
109	35	robfinch	`endif
110	32	robfinch	`4'hE: ;`
111			`4'hF: ;`
112			`default: ;`
113	20	robfinch	`endcase`
114			`end`
115	32	robfinch	`ASL_ACC: Rt <= 4'd1;
116			`ROL_ACC: Rt <= 4'd1;
117			`LSR_ACC: Rt <= 4'd1;
118			`ROR_ACC: Rt <= 4'd1;
119	20	robfinch
120			`RR:
121			`begin`
122	30	robfinch	`Rt <= ir[19:16];`
123	20	robfinch	`case(ir[23:20])`
124	32	robfinch	`ADD_RR: b <= rfob;
125			`SUB_RR: b <= rfob;
126			`AND_RR: b <= rfob; // for bit flags
127			`OR_RR: b <= rfob;
128			`EOR_RR: b <= rfob;
129			`MUL_RR: begin b <= rfob; state <= MULDIV1; end
130			`MULS_RR: begin b <= rfob; state <= MULDIV1; end
131	30	robfinch	`ifdef SUPPORT_DIVMOD
132	32	robfinch	`DIV_RR: begin b <= rfob; state <= MULDIV1; end
133			`DIVS_RR: begin b <= rfob; state <= MULDIV1; end
134			`MOD_RR: begin b <= rfob; state <= MULDIV1; end
135			`MODS_RR: begin b <= rfob; state <= MULDIV1; end
136	30	robfinch	`endif
137			`ifdef SUPPORT_SHIFT
138			`ASL_RRR: begin b <= rfob; state <= CALC; end
139			`LSR_RRR: begin b <= rfob; state <= CALC; end
140			`endif
141			`default:`
142			`begin`
143			`Rt <= 4'h0;`
144	32	robfinch	pg2 <= `FALSE;
145	30	robfinch	ir <= {8{`BRK}};
146			hwi <= `TRUE;
147			`vect <= {vbr[31:9],9'd495,2'b00};`
148			`pc <= pc; // override the pc increment`
149			`state <= DECODE;`
150			`end`
151	20	robfinch	`endcase`
152			`end`
153	32	robfinch	`LD_RR: Rt <= ir[15:12];
154			`ASL_RR: Rt <= ir[15:12];
155			`ROL_RR: Rt <= ir[15:12];
156			`LSR_RR: Rt <= ir[15:12];
157			`ROR_RR: Rt <= ir[15:12];
158			`DEC_RR: Rt <= ir[15:12];
159			`INC_RR: Rt <= ir[15:12];
160	20	robfinch
161	32	robfinch	`ADD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
162			`SUB_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
163			`MUL_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
164			`ifdef SUPPORT_DIVMOD
165			`DIV_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
166			`MOD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
167			`endif
168			`OR_IMM8: begin Rt <= ir[15:12]; end
169			`AND_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
170			`EOR_IMM8: begin Rt <= ir[15:12]; end
171			`CMP_IMM8: ;
172	30	robfinch	`ifdef SUPPORT_SHIFT
173	32	robfinch	`ASL_IMM8: begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
174			`LSR_IMM8: begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
175	30	robfinch	`endif
176	32	robfinch
177			`ADD_IMM16: begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
178			`SUB_IMM16: begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
179			`MUL_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
180			`ifdef SUPPORT_DIVMOD
181			`DIV_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
182			`MOD_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
183			`endif
184			`OR_IMM16: begin Rt <= ir[15:12]; end
185			`AND_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
186			`EOR_IMM16: begin Rt <= ir[15:12]; end
187	20	robfinch
188	32	robfinch	`ADD_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
189			`SUB_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
190			`MUL_IMM16: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
191			`ifdef SUPPORT_DIVMOD
192			`DIV_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
193			`MOD_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
194			`endif
195			`OR_IMM32: begin Rt <= ir[15:12]; end
196			`AND_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
197			`EOR_IMM32: begin Rt <= ir[15:12]; end
198	20	robfinch
199	32	robfinch	`LDA_IMM32: Rt <= 4'd1;
200			`LDX_IMM32: Rt <= 4'd2;
201			`LDY_IMM32: Rt <= 4'd3;
202			`LDA_IMM16: Rt <= 4'd1;
203			`LDX_IMM16: Rt <= 4'd2;
204			`LDA_IMM8: Rt <= 4'd1;
205			`LDX_IMM8: Rt <= 4'd2;
206	20	robfinch
207	32	robfinch	`SUB_SP8: ;
208			`SUB_SP16: ;
209			`SUB_SP32: ;
210	23	robfinch
211	32	robfinch	`CPX_IMM32: ;
212			`CPY_IMM32: ;
213	30	robfinch
214	32	robfinch	`LDX_ZPX:
215	20	robfinch	`begin`
216	32	robfinch	`Rt <= 4'd2;`
217	20	robfinch	`radr <= zpx32xy_address;`
218	21	robfinch	load_what <= `WORD_311;
219			`state <= LOAD_MAC1;`
220	20	robfinch	`end`
221	32	robfinch	`LDY_ZPX:
222			`begin`
223			`Rt <= 4'd3;`
224			`radr <= zpx32xy_address;`
225			load_what <= `WORD_311;
226			`state <= LOAD_MAC1;`
227			`end`
228	20	robfinch	`ORB_ZPX:
229			`begin`
230			`Rt <= ir[19:16];`
231			`radr <= zpx32_address[31:2];`
232			`radr2LSB <= zpx32_address[1:0];`
233	21	robfinch	load_what <= `WORD_310;
234			`state <= LOAD_MAC1;`
235	20	robfinch	`end`
236	32	robfinch	`LDX_ABS:
237	20	robfinch	`begin`
238	32	robfinch	`Rt <= 4'd2;`
239	20	robfinch	`radr <= ir[39:8];`
240	21	robfinch	load_what <= `WORD_311;
241			`state <= LOAD_MAC1;`
242	20	robfinch	`end`
243	32	robfinch	`LDY_ABS:
244			`begin`
245			`Rt <= 4'd3;`
246			`radr <= ir[39:8];`
247			load_what <= `WORD_311;
248			`state <= LOAD_MAC1;`
249			`end`
250	20	robfinch	`ORB_ABS:
251			`begin`
252			`Rt <= ir[15:12];`
253			`radr <= ir[47:18];`
254			`radr2LSB <= ir[17:16];`
255	21	robfinch	load_what <= `WORD_310;
256			`state <= LOAD_MAC1;`
257	20	robfinch	`end`
258	32	robfinch	`LDX_ABSY:
259	20	robfinch	`begin`
260	32	robfinch	`Rt <= 4'd2;`
261	20	robfinch	`radr <= absx32xy_address;`
262	21	robfinch	load_what <= `WORD_311;
263			`state <= LOAD_MAC1;`
264	20	robfinch	`end`
265	32	robfinch	`LDY_ABSX:
266			`begin`
267			`Rt <= 4'd3;`
268			`radr <= absx32xy_address;`
269			load_what <= `WORD_311;
270			`state <= LOAD_MAC1;`
271			`end`
272	20	robfinch	`ORB_ABSX:
273			`begin`
274			`Rt <= ir[19:16];`
275			`radr <= absx32_address[31:2];`
276			`radr2LSB <= absx32_address[1:0];`
277	21	robfinch	load_what <= `WORD_310;
278			`state <= LOAD_MAC1;`
279	20	robfinch	`end`
280			`ST_ZPX:
281			`begin`
282			`wadr <= zpx32_address;`
283	30	robfinch	store_what <= `STW_RFA;
284	20	robfinch	`state <= STORE1;`
285			`end`
286			`STB_ZPX:
287			`begin`
288			`wadr <= zpx32_address[31:2];`
289			`wadr2LSB <= zpx32_address[1:0];`
290	30	robfinch	store_what <= `STW_RFA8;
291	20	robfinch	`state <= STORE1;`
292			`end`
293	23	robfinch	`ST_DSP:
294			`begin`
295			`wadr <= {{24{ir[23]}},ir[23:16]} + isp;`
296	30	robfinch	store_what <= `STW_RFA;
297	23	robfinch	`state <= STORE1;`
298			`end`
299	20	robfinch	`ST_ABS:
300			`begin`
301			`wadr <= ir[47:16];`
302	30	robfinch	store_what <= `STW_RFA;
303	20	robfinch	`state <= STORE1;`
304			`end`
305			`STB_ABS:
306			`begin`
307			`wadr <= ir[47:18];`
308			`wadr2LSB <= ir[17:16];`
309	30	robfinch	store_what <= `STW_RFA8;
310	20	robfinch	`state <= STORE1;`
311			`end`
312			`ST_ABSX:
313			`begin`
314			`wadr <= absx32_address;`
315	30	robfinch	store_what <= `STW_RFA;
316	20	robfinch	`state <= STORE1;`
317			`end`
318			`STB_ABSX:
319			`begin`
320			`wadr <= absx32_address[31:2];`
321			`wadr2LSB <= absx32_address[1:0];`
322	30	robfinch	store_what <= `STW_RFA8;
323	20	robfinch	`state <= STORE1;`
324			`end`
325			`STX_ZPX:
326			`begin`
327	30	robfinch	`wadr <= zpx32xy_address;`
328			store_what <= `STW_X;
329	20	robfinch	`state <= STORE1;`
330			`end`
331			`STX_ABS:
332			`begin`
333			`wadr <= ir[39:8];`
334	30	robfinch	store_what <= `STW_X;
335	20	robfinch	`state <= STORE1;`
336			`end`
337			`STY_ZPX:
338			`begin`
339	30	robfinch	`wadr <= zpx32xy_address;`
340			store_what <= `STW_Y;
341	20	robfinch	`state <= STORE1;`
342			`end`
343			`STY_ABS:
344			`begin`
345			`wadr <= ir[39:8];`
346	30	robfinch	store_what <= `STW_Y;
347	20	robfinch	`state <= STORE1;`
348			`end`
349	36	robfinch	`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`TRB_ZPX:
350	20	robfinch	`begin`
351			`Rt <= ir[19:16];`
352			`radr <= zpx32_address;`
353	21	robfinch	load_what <= `WORD_310;
354			`state <= LOAD_MAC1;`
355	20	robfinch	`end`
356	36	robfinch	`LEA_ZPX:
357			`begin`
358			`Rt <= ir[19:16];`
359			`res <= zpx32_address;`
360			`state <= IFETCH;`
361			`end`
362	32	robfinch	`// Trim a clock cycle off of loads by testing for Ra = 0.`
363	36	robfinch	`OR_ZPX,`EOR_ZPX,`TSB_ZPX:
364	32	robfinch	`begin`
365			`Rt <= ir[19:16];`
366			`radr <= zpx32_address;`
367			load_what <= (Ra==4'd0) ? `WORD_311: `WORD_310;
368			`state <= LOAD_MAC1;`
369			`end`
370	20	robfinch	`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
371			`begin`
372	30	robfinch	`radr <= zpx32xy_address;`
373	21	robfinch	load_what <= `WORD_310;
374			`state <= LOAD_MAC1;`
375	20	robfinch	`end`
376	32	robfinch	`BMS_ZPX,`BMC_ZPX,`BMF_ZPX,`BMT_ZPX:
377			`begin`
378			`radr <= zpx32xy_address + acc[31:5];`
379			load_what <= `WORD_310;
380			`state <= LOAD_MAC1;`
381			`end`
382	36	robfinch	`LEA_DSP:
383			`begin`
384			`Rt <= ir[15:12];`
385			`res <= {{24{ir[23]}},ir[23:16]} + isp;`
386			`state <= IFETCH;`
387			`end`
388	23	robfinch	`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
389			`begin`
390			`Rt <= ir[15:12];`
391			`radr <= {{24{ir[23]}},ir[23:16]} + isp;`
392			load_what <= `WORD_310;
393			`state <= LOAD_MAC1;`
394			`end`
395	36	robfinch	`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX,`LEA_IX:
396	20	robfinch	`begin`
397	25	robfinch	if (ir[7:0]!=`ST_IX) // for ST_IX, Rt=0
398	20	robfinch	`Rt <= ir[19:16];`
399	30	robfinch	`radr <= zpx32_address;`
400	21	robfinch	load_what <= `IA_310;
401	30	robfinch	store_what <= `STW_A;
402	21	robfinch	`state <= LOAD_MAC1;`
403	20	robfinch	`end`
404	36	robfinch	`LEA_RIND:
405			`begin`
406			`Rt <= ir[19:16];`
407			`res <= rfob;`
408			`state <= IFETCH;`
409			`end`
410	25	robfinch	`ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
411	20	robfinch	`begin`
412			`radr <= rfob;`
413	25	robfinch	`Rt <= ir[19:16];`
414			load_what <= `WORD_310;
415			`state <= LOAD_MAC1;`
416	20	robfinch	`end`
417	25	robfinch	`ST_RIND:
418			`begin`
419			`wadr <= rfob;`
420	30	robfinch	store_what <= `STW_RFA;
421	25	robfinch	`state <= STORE1;`
422			`end`
423	36	robfinch	`ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY,`LEA_IY:
424	20	robfinch	`begin`
425	25	robfinch	if (ir[7:0]!=`ST_IY) // for ST_IY, Rt=0
426	20	robfinch	`Rt <= ir[19:16];`
427	21	robfinch	`isIY <= 1'b1;`
428	30	robfinch	`radr <= ir[31:20];`
429	21	robfinch	load_what <= `IA_310;
430	30	robfinch	store_what <= `STW_A;
431	21	robfinch	`state <= LOAD_MAC1;`
432	20	robfinch	`end`
433	36	robfinch	`LEA_ABS:
434	20	robfinch	`begin`
435	36	robfinch	`res <= ir[47:16];`
436			`Rt <= ir[15:12];`
437			`state <= IFETCH;`
438			`end`
439			`OR_ABS,`EOR_ABS,`TSB_ABS:
440			`begin`
441	20	robfinch	`radr <= ir[47:16];`
442			`Rt <= ir[15:12];`
443	32	robfinch	load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
444			`state <= LOAD_MAC1;`
445			`end`
446	36	robfinch	`ADD_ABS,`SUB_ABS,`AND_ABS,`TRB_ABS:
447	32	robfinch	`begin`
448			`radr <= ir[47:16];`
449			`Rt <= ir[15:12];`
450	21	robfinch	load_what <= `WORD_310;
451			`state <= LOAD_MAC1;`
452	20	robfinch	`end`
453			`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS:
454			`begin`
455			`radr <= ir[39:8];`
456	21	robfinch	load_what <= `WORD_310;
457			`state <= LOAD_MAC1;`
458	20	robfinch	`end`
459	32	robfinch	`BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS:
460	20	robfinch	`begin`
461	32	robfinch	`radr <= ir[39:8] + acc[31:5];`
462			load_what <= `WORD_310;
463			`state <= LOAD_MAC1;`
464			`end`
465	36	robfinch	`LEA_ABSX:
466			`begin`
467			`res <= absx32_address;`
468			`Rt <= ir[19:16];`
469			`state <= IFETCH;`
470			`end`
471	32	robfinch	`ADD_ABSX,`SUB_ABSX,`AND_ABSX:
472			`begin`
473	30	robfinch	`radr <= absx32_address;`
474	20	robfinch	`Rt <= ir[19:16];`
475	21	robfinch	load_what <= `WORD_310;
476			`state <= LOAD_MAC1;`
477	20	robfinch	`end`
478	32	robfinch	`OR_ABSX,`EOR_ABSX:
479			`begin`
480			`radr <= absx32_address;`
481			`Rt <= ir[19:16];`
482			load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
483			`state <= LOAD_MAC1;`
484			`end`
485	20	robfinch	`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
486			`begin`
487	30	robfinch	`radr <= absx32xy_address;`
488	21	robfinch	load_what <= `WORD_310;
489			`state <= LOAD_MAC1;`
490	20	robfinch	`end`
491	32	robfinch	`BMS_ABSX,`BMC_ABSX,`BMF_ABSX,`BMT_ABSX:
492			`begin`
493			`radr <= absx32xy_address + acc[31:5];`
494			load_what <= `WORD_310;
495			`state <= LOAD_MAC1;`
496			`end`
497	30	robfinch
498	20	robfinch	`CPX_ZPX:
499			`begin`
500	30	robfinch	`radr <= zpx32xy_address;`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [decode.v] - Blame information for rev 37