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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
IFETCH:
        begin
                vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
                suppress_pcinc <= 4'hF;                         // default: no suppression of increment
                opc <= pc;
                hwi <= `FALSE;
                isBusErr <= `FALSE;
                pg2 <= `FALSE;
                store_what <= `STW_DEF;
                if (nmi_edge & gie & !isExec & !isAtni) begin
                        ir[7:0] <= `BRK;
                        nmi_edge <= 1'b0;
                        wai <= 1'b0;
                        hwi <= `TRUE;
                        next_state(DECODE);
                        vect <= `NMI_VECT;
                end
                else if (irq_i & gie & !isExec & !isAtni) begin
                        wai <= 1'b0;
                        if (im) begin
                                if (ttrig) begin
                                        ir[7:0] <= `BRK;
                                        vect <= {vbr[31:9],9'd490,2'b00};
                                        next_state(DECODE);
                                end
                                else if (isExec) begin
                                        ir <= exbuf;
                                        exbuf <= 64'd0;
                                        suppress_pcinc <= 4'h0;
                                        next_state(DECODE);
                                end
                                else if (unCachedInsn) begin
                                        if (bhit) begin
                                                ir <= ibuf + exbuf;
                                                exbuf <= 64'd0;
                                                next_state(DECODE);
                                        end
                                        else begin
                                                pg2 <= pg2;
                                                state <= LOAD_IBUF1;
                                        end
                                end
                                else begin
                                        if (ihit) begin
                                                ir <= insn + exbuf;
                                                exbuf <= 64'd0;
                                                next_state(DECODE);
                                        end
                                        else begin
                                                pg2 <= pg2;
                                                state <= ICACHE1;
                                        end
                                end
                        end
                        else begin
                                ir[7:0] <= `BRK;
                                hwi <= `TRUE;
                                vect <= {vbr[31:9],irq_vect,2'b00};
                                next_state(DECODE);
                        end
                end
                else if (!wai) begin
                        if (ttrig) begin
                                ir[7:0] <= `BRK;
                                vect <= {vbr[31:9],9'd490,2'b00};
                                next_state(DECODE);
                        end
                        else if (isExec) begin
                                ir <= exbuf;
                                exbuf <= 64'd0;
                                suppress_pcinc <= 4'h0;
                                next_state(DECODE);
                        end
                        else if (unCachedInsn) begin
                                if (bhit) begin
                                        ir <= ibuf + exbuf;
                                        exbuf <= 64'd0;
                                        next_state(DECODE);
                                end
                                else begin
                                        pg2 <= pg2;
                                        state <= LOAD_IBUF1;
                                end
                        end
                        else begin
                                if (ihit) begin
                                        ir <= insn + exbuf;
                                        exbuf <= 64'd0;
                                        next_state(DECODE);
                                end
                                else begin
                                        pg2 <= pg2;
                                        next_state(ICACHE1);
                                end
                        end
                end
                // During a cache miss all these assignments will repeat. It's not a
                // problem. The history buffer will be stuffed with the same pc address
                // for several cycles until the cache load is complete.
`ifdef DEBUG
                if (hist_capture) begin
                        history_buf[history_ndx] <= pc;
                        history_ndx <= history_ndx+7'd1;
                end
`endif
                case(ir9)
                `TAS,`TXS:      begin isp <= res[31:0]; gie <= 1'b1; end
                `SUB_SP8,`SUB_SP16,`SUB_SP32:   isp <= res[31:0];
                `TRS:
                        begin
                                case(ir[15:12])
                                4'h0:   begin
                                                $display("res=%h",res);
`ifdef SUPPORT_ICACHE
                                                icacheOn <= res[0];
`endif
`ifdef SUPPORT_DCACHE
                                                dcacheOn <= res[1];
                                                write_allocate <= res[2];
`endif
                                                end
                                4'h5:   lfsr <= res[31:0];
                                4'h7:   abs8 <= res[31:0];
                                4'h8:   begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end
                                4'hE:   begin sp <= res[7:0]; spage[31:8] <= res[31:8]; end
                                4'hF:   begin isp <= res[31:0]; gie <= 1'b1; end
                                endcase
                        end
                `RR:
                        case(ir[23:20])
                        `ADD_RR:        begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
                        `SUB_RR:
                                        if (Rt==4'h0)   // CMP doesn't set overflow
                                                begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                                        else
                                                begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
                        `AND_RR:
                                if (Rt==4'h0)   // BIT sets overflow
                                        begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
                                else
                                        begin nf <= resn32; zf <= resz32; end
                        default:
                                        begin nf <= resn32; zf <= resz32; end
                        endcase
                `LD_RR: begin zf <= resz32; nf <= resn32; end
                `DEC_RR,`INC_RR: begin zf <= resz32; nf <= resn32; end
                `ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
                        begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
                `SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
                        if (Rt==4'h0)   // CMP doesn't set overflow
                                begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                        else
                                begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
`ifdef SUPPORT_DIVMOD
                `DIV_IMM8,`DIV_IMM16,`DIV_IMM32,
                `MOD_IMM8,`MOD_IMM16,`MOD_IMM32,
`endif
                `MUL_IMM8,`MUL_IMM16,`MUL_IMM32:
                        begin nf <= resn32; zf <= resz32; end
                `AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:
                        if (Rt==4'h0)   // BIT sets overflow
                                begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
                        else
                                begin nf <= resn32; zf <= resz32; end
                `ORB_ZPX,`ORB_ABS,`ORB_ABSX,
                `OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
                `EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
                        begin nf <= resn32; zf <= resz32; end
                `ASL_ACC,`ROL_ACC,`LSR_ACC,`ROR_ACC:
                        begin cf <= resc32; nf <= resn32; zf <= resz32; end
                `ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,
                `ASL_ZPX,`ASL_ABS,`ASL_ABSX,
                `ROL_ZPX,`ROL_ABS,`ROL_ABSX,
                `LSR_ZPX,`LSR_ABS,`LSR_ABSX,
                `ROR_ZPX,`ROR_ABS,`ROR_ABSX:
                        begin cf <= resc32; nf <= resn32; zf <= resz32; end
                `ASL_IMM8: begin nf <= resn32; zf <= resz32; end
                `LSR_IMM8: begin nf <= resn32; zf <= resz32; end
                `BMT_ZPX,`BMT_ABS,`BMT_ABSX: begin nf <= resn32; zf <= resz32; end
                `INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn32; zf <= resz32; end
                `DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn32; zf <= resz32; end
                `TAX,`TYX,`TSX,`DEX,`INX,
                `LDX_IMM32,`LDX_IMM16,`LDX_IMM8,`LDX_ZPY,`LDX_ABS,`LDX_ABSY,`PLX:
                        begin nf <= resn32; zf <= resz32; end
                `TAY,`TXY,`DEY,`INY,
                `LDY_IMM32,`LDY_ZPX,`LDY_ABS,`LDY_ABSX,`PLY:
                        begin nf <= resn32; zf <= resz32; end
                `CPX_IMM32,`CPX_ZPX,`CPX_ABS:   begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                `CPY_IMM32,`CPY_ZPX,`CPY_ABS:   begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                `CMP_IMM8: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                `TSA,`TYA,`TXA,`INA,`DEA,
                `LDA_IMM32,`LDA_IMM16,`LDA_IMM8,`PLA:   begin nf <= resn32; zf <= resz32; end
                `POP:   begin nf <= resn32; zf <= resz32; end
                `TRB_ZPX,`TRB_ABS,`TSB_ZPX,`TSB_ABS:
                        begin zf <= resz32; end
                `BMT_ZPX,`BMT_ABS,`BMT_ABSX:
                        begin zf <= resz32; nf <= resn32; end
                endcase
        end

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23			`IFETCH:`
24			`begin`
25	32	robfinch	vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
26	25	robfinch	`suppress_pcinc <= 4'hF; // default: no suppression of increment`
27	23	robfinch	`opc <= pc;`
28	25	robfinch	hwi <= `FALSE;
29	32	robfinch	isBusErr <= `FALSE;
30			pg2 <= `FALSE;
31	30	robfinch	store_what <= `STW_DEF;
32	35	robfinch	`if (nmi_edge & gie & !isExec & !isAtni) begin`
33	32	robfinch	ir[7:0] <= `BRK;
34	20	robfinch	`nmi_edge <= 1'b0;`
35			`wai <= 1'b0;`
36	25	robfinch	hwi <= `TRUE;
37	35	robfinch	`next_state(DECODE);`
38	32	robfinch	vect <= `NMI_VECT;
39	20	robfinch	`end`
40	32	robfinch	`else if (irq_i & gie & !isExec & !isAtni) begin`
41	30	robfinch	`wai <= 1'b0;`
42	20	robfinch	`if (im) begin`
43	32	robfinch	`if (ttrig) begin`
44			ir[7:0] <= `BRK;
45			`vect <= {vbr[31:9],9'd490,2'b00};`
46	35	robfinch	`next_state(DECODE);`
47	32	robfinch	`end`
48			`else if (isExec) begin`
49	25	robfinch	`ir <= exbuf;`
50			`exbuf <= 64'd0;`
51			`suppress_pcinc <= 4'h0;`
52	35	robfinch	`next_state(DECODE);`
53	25	robfinch	`end`
54			`else if (unCachedInsn) begin`
55	20	robfinch	`if (bhit) begin`
56	25	robfinch	`ir <= ibuf + exbuf;`
57			`exbuf <= 64'd0;`
58	35	robfinch	`next_state(DECODE);`
59	20	robfinch	`end`
60	35	robfinch	`else begin`
61			`pg2 <= pg2;`
62	32	robfinch	`state <= LOAD_IBUF1;`
63	35	robfinch	`end`
64	20	robfinch	`end`
65			`else begin`
66			`if (ihit) begin`
67	25	robfinch	`ir <= insn + exbuf;`
68			`exbuf <= 64'd0;`
69	35	robfinch	`next_state(DECODE);`
70	20	robfinch	`end`
71	35	robfinch	`else begin`
72			`pg2 <= pg2;`
73	32	robfinch	`state <= ICACHE1;`
74	35	robfinch	`end`
75	20	robfinch	`end`
76			`end`
77			`else begin`
78	32	robfinch	ir[7:0] <= `BRK;
79	25	robfinch	hwi <= `TRUE;
80	32	robfinch	`vect <= {vbr[31:9],irq_vect,2'b00};`
81	35	robfinch	`next_state(DECODE);`
82	20	robfinch	`end`
83			`end`
84			`else if (!wai) begin`
85	32	robfinch	`if (ttrig) begin`
86			ir[7:0] <= `BRK;
87			`vect <= {vbr[31:9],9'd490,2'b00};`
88	35	robfinch	`next_state(DECODE);`
89	32	robfinch	`end`
90			`else if (isExec) begin`
91	25	robfinch	`ir <= exbuf;`
92			`exbuf <= 64'd0;`
93			`suppress_pcinc <= 4'h0;`
94	35	robfinch	`next_state(DECODE);`
95	25	robfinch	`end`
96			`else if (unCachedInsn) begin`
97	20	robfinch	`if (bhit) begin`
98	25	robfinch	`ir <= ibuf + exbuf;`
99			`exbuf <= 64'd0;`
100	35	robfinch	`next_state(DECODE);`
101	20	robfinch	`end`
102	35	robfinch	`else begin`
103			`pg2 <= pg2;`
104	32	robfinch	`state <= LOAD_IBUF1;`
105	35	robfinch	`end`
106	20	robfinch	`end`
107			`else begin`
108			`if (ihit) begin`
109	25	robfinch	`ir <= insn + exbuf;`
110			`exbuf <= 64'd0;`
111	35	robfinch	`next_state(DECODE);`
112	20	robfinch	`end`
113	35	robfinch	`else begin`
114			`pg2 <= pg2;`
115			`next_state(ICACHE1);`
116			`end`
117	20	robfinch	`end`
118			`end`
119	32	robfinch	`// During a cache miss all these assignments will repeat. It's not a`
120			`// problem. The history buffer will be stuffed with the same pc address`
121			`// for several cycles until the cache load is complete.`
122	35	robfinch	`ifdef DEBUG
123	32	robfinch	`if (hist_capture) begin`
124			`history_buf[history_ndx] <= pc;`
125			`history_ndx <= history_ndx+7'd1;`
126			`end`
127	35	robfinch	`endif
128	32	robfinch	`case(ir9)`
129	35	robfinch	`TAS,`TXS: begin isp <= res[31:0]; gie <= 1'b1; end
130			`SUB_SP8,`SUB_SP16,`SUB_SP32: isp <= res[31:0];
131	32	robfinch	`TRS:
132	30	robfinch	`begin`
133	32	robfinch	`case(ir[15:12])`
134			`4'h0: begin`
135			`$display("res=%h",res);`
136	30	robfinch	`ifdef SUPPORT_ICACHE
137	32	robfinch	`icacheOn <= res[0];`
138	30	robfinch	`endif
139			`ifdef SUPPORT_DCACHE
140	32	robfinch	`dcacheOn <= res[1];`
141			`write_allocate <= res[2];`
142	30	robfinch	`endif
143	32	robfinch	`end`
144	35	robfinch	`4'h5: lfsr <= res[31:0];`
145			`4'h7: abs8 <= res[31:0];`
146	32	robfinch	`4'h8: begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end`
147			`4'hE: begin sp <= res[7:0]; spage[31:8] <= res[31:8]; end`
148	35	robfinch	`4'hF: begin isp <= res[31:0]; gie <= 1'b1; end`
149	32	robfinch	`endcase`
150			`end`
151			`RR:
152			`case(ir[23:20])`
153			`ADD_RR: begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
154			`SUB_RR:
155	20	robfinch	`if (Rt==4'h0) // CMP doesn't set overflow`
156			`begin cf <= ~resc32; nf <= resn32; zf <= resz32; end`
157			`else`
158			`begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end`
159	32	robfinch	`AND_RR:
160			`if (Rt==4'h0) // BIT sets overflow`
161			`begin nf <= b[31]; vf <= b[30]; zf <= resz32; end`
162			`else`
163	20	robfinch	`begin nf <= resn32; zf <= resz32; end`
164	32	robfinch	`default:`
165			`begin nf <= resn32; zf <= resz32; end`
166			`endcase`
167			`LD_RR: begin zf <= resz32; nf <= resn32; end
168			`DEC_RR,`INC_RR: begin zf <= resz32; nf <= resn32; end
169			`ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
170			`begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end`
171			`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
172			`if (Rt==4'h0) // CMP doesn't set overflow`
173			`begin cf <= ~resc32; nf <= resn32; zf <= resz32; end`
174			`else`
175			`begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end`
176			`ifdef SUPPORT_DIVMOD
177			`DIV_IMM8,`DIV_IMM16,`DIV_IMM32,
178			`MOD_IMM8,`MOD_IMM16,`MOD_IMM32,
179			`endif
180			`MUL_IMM8,`MUL_IMM16,`MUL_IMM32:
181			`begin nf <= resn32; zf <= resz32; end`
182			`AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:
183			`if (Rt==4'h0) // BIT sets overflow`
184			`begin nf <= b[31]; vf <= b[30]; zf <= resz32; end`
185			`else`
186			`begin nf <= resn32; zf <= resz32; end`
187			`ORB_ZPX,`ORB_ABS,`ORB_ABSX,
188			`OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
189			`EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
190			`begin nf <= resn32; zf <= resz32; end`
191			`ASL_ACC,`ROL_ACC,`LSR_ACC,`ROR_ACC:
192			`begin cf <= resc32; nf <= resn32; zf <= resz32; end`
193			`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,
194			`ASL_ZPX,`ASL_ABS,`ASL_ABSX,
195			`ROL_ZPX,`ROL_ABS,`ROL_ABSX,
196			`LSR_ZPX,`LSR_ABS,`LSR_ABSX,
197			`ROR_ZPX,`ROR_ABS,`ROR_ABSX:
198			`begin cf <= resc32; nf <= resn32; zf <= resz32; end`
199			`ASL_IMM8: begin nf <= resn32; zf <= resz32; end
200			`LSR_IMM8: begin nf <= resn32; zf <= resz32; end
201			`BMT_ZPX,`BMT_ABS,`BMT_ABSX: begin nf <= resn32; zf <= resz32; end
202			`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn32; zf <= resz32; end
203			`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn32; zf <= resz32; end
204			`TAX,`TYX,`TSX,`DEX,`INX,
205			`LDX_IMM32,`LDX_IMM16,`LDX_IMM8,`LDX_ZPY,`LDX_ABS,`LDX_ABSY,`PLX:
206			`begin nf <= resn32; zf <= resz32; end`
207			`TAY,`TXY,`DEY,`INY,
208			`LDY_IMM32,`LDY_ZPX,`LDY_ABS,`LDY_ABSX,`PLY:
209			`begin nf <= resn32; zf <= resz32; end`
210			`CPX_IMM32,`CPX_ZPX,`CPX_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
211			`CPY_IMM32,`CPY_ZPX,`CPY_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
212			`CMP_IMM8: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
213			`TSA,`TYA,`TXA,`INA,`DEA,
214			`LDA_IMM32,`LDA_IMM16,`LDA_IMM8,`PLA: begin nf <= resn32; zf <= resz32; end
215			`POP: begin nf <= resn32; zf <= resz32; end
216	36	robfinch	`TRB_ZPX,`TRB_ABS,`TSB_ZPX,`TSB_ABS:
217			`begin zf <= resz32; end`
218			`BMT_ZPX,`BMT_ABS,`BMT_ABSX:
219			`begin zf <= resz32; nf <= resn32; end`
220	32	robfinch	`endcase`
221	20	robfinch	`end`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [ifetch.v] - Blame information for rev 36