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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
IFETCH:
        begin
                ic_whence <= IFETCH;
                vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
                suppress_pcinc <= 4'hF;                         // default: no suppression of increment
                opc <= pc;
                hwi <= `FALSE;
                isBusErr <= `FALSE;
                pg2 <= `FALSE;
                isIY <= `FALSE;
                isIY24 <= `FALSE;
                store_what <= `STW_DEF;
                if (nmi_edge & gie & !isExec & !isAtni) begin
                        ir[7:0] <= `BRK;
                        nmi_edge <= 1'b0;
                        wai <= 1'b0;
                        hwi <= `TRUE;
                        next_state(DECODE);
                        vect <= `NMI_VECT;
                end
                else if ((irq_i|spi) & gie & !isExec & !isAtni) begin
                        wai <= 1'b0;
                        if (im) begin
                                if (ttrig) begin
                                        ir[7:0] <= `BRK;
                                        vect <= {vbr[31:9],9'd490,2'b00};
                                        next_state(DECODE);
                                end
                                else if (isExec) begin
                                        ir <= exbuf;
                                        exbuf <= 64'd0;
                                        suppress_pcinc <= 4'h0;
                                        next_state(DECODE);
                                end
                                else if (unCachedInsn) begin
                                        if (bhit) begin
                                                ir <= ibuf + exbuf;
                                                exbuf <= 64'd0;
                                                next_state(DECODE);
                                        end
                                        else begin
                                                pg2 <= pg2;
                                                state <= LOAD_IBUF1;
                                        end
                                end
                                else begin
                                        if (ihit) begin
                                                ir <= insn + exbuf;
                                                exbuf <= 64'd0;
                                                next_state(DECODE);
                                        end
                                        else begin
                                                pg2 <= pg2;
                                                next_state(ICACHE1);
                                        end
                                end
                        end
                        else begin
                                ir[7:0] <= `BRK;
                                hwi <= `TRUE;
                                if (spi) begin
                                        spi <= 1'b0;
                                        spi_cnt <= SPIN_CYCLES;
                                        vect <= {vbr[31:9],9'd3,2'b00};
                                end
                                else begin
                                        vect <= {vbr[31:9],irq_vect,2'b00};
                                end
                                next_state(DECODE);
                        end
                end
                else if (!wai) begin
                        if (ttrig) begin
                                ir[7:0] <= `BRK;
                                vect <= {vbr[31:9],9'd490,2'b00};
                                next_state(DECODE);
                        end
                        else if (isExec) begin
                                ir <= exbuf;
                                exbuf <= 64'd0;
                                suppress_pcinc <= 4'h0;
                                next_state(DECODE);
                        end
                        else if (unCachedInsn) begin
                                if (bhit) begin
                                        ir <= ibuf + exbuf;
                                        exbuf <= 64'd0;
                                        next_state(DECODE);
                                end
                                else begin
                                        pg2 <= pg2;
                                        state <= LOAD_IBUF1;
                                end
                        end
                        else begin
                                if (ihit) begin
                                        ir <= insn + exbuf;
                                        exbuf <= 64'd0;
                                        next_state(DECODE);
                                end
                                else begin
                                        pg2 <= pg2;
                                        next_state(ICACHE1);
                                end
                        end
                end
                // During a cache miss all these assignments will repeat. It's not a
                // problem. The history buffer will be stuffed with the same pc address
                // for several cycles until the cache load is complete.
`ifdef DEBUG
                if (hist_capture) begin
                        history_buf[history_ndx] <= pc;
                        history_ndx <= history_ndx+7'd1;
                end
`endif
                case(ir9)
                `TAS,`TXS:      begin isp <= res[31:0]; gie <= 1'b1; end
                `SUB_SP8,`SUB_SP16,`SUB_SP32:   isp <= res[31:0];
                `TRS:
                        begin
                                case(ir[15:12])
                                4'h0:   begin
                                                $display("res=%h",res);
`ifdef SUPPORT_ICACHE
                                                icacheOn <= res[0];
`endif
`ifdef SUPPORT_DCACHE
                                                dcacheOn <= res[1];
                                                write_allocate <= res[2];
`endif
                                                end
                                4'h5:   lfsr <= res[31:0];
                                4'h7:   abs8 <= res[31:0];
                                4'h8:   begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end
                                4'hE:   begin sp <= res[15:0]; spage[31:16] <= res[31:16]; end
                                4'hF:   begin isp <= res[31:0]; gie <= 1'b1; end
                                endcase
                        end
                `RR:
                        case(ir[23:20])
                        `ADD_RR:        begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
                        `SUB_RR:
                                        if (Rt==4'h0)   // CMP doesn't set overflow
                                                begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                                        else
                                                begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
                        `AND_RR:
                                if (Rt==4'h0)   // BIT sets overflow
                                        begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
                                else
                                        begin nf <= resn32; zf <= resz32; end
                        default:
                                        begin nf <= resn32; zf <= resz32; end
                        endcase
                `LD_RR: begin zf <= resz32; nf <= resn32; end
                `DEC_RR,`INC_RR: begin zf <= resz32; nf <= resn32; end
                `ADD_IMM4,`ADD_R,
                `ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
                        begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
                `SUB_IMM4,`SUB_R,
                `SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
                        if (Rt==4'h0)   // CMP doesn't set overflow
                                begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                        else
                                begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
`ifdef SUPPORT_DIVMOD
                `DIV_IMM8,`DIV_IMM16,`DIV_IMM32,
                `MOD_IMM8,`MOD_IMM16,`MOD_IMM32,
`endif
                `MUL_IMM8,`MUL_IMM16,`MUL_IMM32:
                        begin nf <= resn32; zf <= resz32; end
                `AND_IMM4,`AND_R,
                `AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:
                        if (Rt==4'h0)   // BIT sets overflow
                                begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
                        else
                                begin nf <= resn32; zf <= resz32; end
                `ORB_ZPX,`ORB_ABS,`ORB_ABSX,
                `OR_IMM4,`OR_R,
                `OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
                `EOR_IMM4,`EOR_R,
                `EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
                        begin nf <= resn32; zf <= resz32; end
                `ASL_ACC,`ROL_ACC,`LSR_ACC,`ROR_ACC:
                        begin cf <= resc32; nf <= resn32; zf <= resz32; end
                `ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,
                `ASL_ZPX,`ASL_ABS,`ASL_ABSX,
                `ROL_ZPX,`ROL_ABS,`ROL_ABSX,
                `LSR_ZPX,`LSR_ABS,`LSR_ABSX,
                `ROR_ZPX,`ROR_ABS,`ROR_ABSX:
                        begin cf <= resc32; nf <= resn32; zf <= resz32; end
                `ASL_IMM8: begin nf <= resn32; zf <= resz32; end
                `LSR_IMM8: begin nf <= resn32; zf <= resz32; end
                `BMT_ZPX,`BMT_ABS,`BMT_ABSX: begin nf <= resn32; zf <= resz32; end
                `INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn32; zf <= resz32; end
                `DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn32; zf <= resz32; end
                `TAX,`TYX,`TSX,`DEX,`INX,
                `LDX_IMM32,`LDX_IMM16,`LDX_IMM8,`LDX_ZPY,`LDX_ABS,`LDX_ABSY,`PLX:
                        begin nf <= resn32; zf <= resz32; end
                `TAY,`TXY,`DEY,`INY,
                `LDY_IMM32,`LDY_ZPX,`LDY_ABS,`LDY_ABSX,`PLY:
                        begin nf <= resn32; zf <= resz32; end
                `CPX_IMM32,`CPX_ZPX,`CPX_ABS:   begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                `CPY_IMM32,`CPY_ZPX,`CPY_ABS:   begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                `CMP_IMM8: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
                `TSA,`TYA,`TXA,`INA,`DEA,
                `LDA_IMM32,`LDA_IMM16,`LDA_IMM8,`PLA:   begin nf <= resn32; zf <= resz32; end
                `POP:   begin nf <= resn32; zf <= resz32; end
                `TRB_ZPX,`TRB_ABS,`TSB_ZPX,`TSB_ABS:
                        begin zf <= resz32; end
                `BMT_ZPX,`BMT_ABS,`BMT_ABSX:
                        begin zf <= resz32; nf <= resn32; end
//              `SPL:   begin if (radr==65002) acc <= 32'h52544600; end
                endcase
        end

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23			`IFETCH:`
24			`begin`
25	38	robfinch	`ic_whence <= IFETCH;`
26	32	robfinch	vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
27	25	robfinch	`suppress_pcinc <= 4'hF; // default: no suppression of increment`
28	23	robfinch	`opc <= pc;`
29	25	robfinch	hwi <= `FALSE;
30	32	robfinch	isBusErr <= `FALSE;
31			pg2 <= `FALSE;
32	38	robfinch	isIY <= `FALSE;
33			isIY24 <= `FALSE;
34	30	robfinch	store_what <= `STW_DEF;
35	35	robfinch	`if (nmi_edge & gie & !isExec & !isAtni) begin`
36	32	robfinch	ir[7:0] <= `BRK;
37	20	robfinch	`nmi_edge <= 1'b0;`
38			`wai <= 1'b0;`
39	25	robfinch	hwi <= `TRUE;
40	35	robfinch	`next_state(DECODE);`
41	32	robfinch	vect <= `NMI_VECT;
42	20	robfinch	`end`
43	38	robfinch	`else if ((irq_i\|spi) & gie & !isExec & !isAtni) begin`
44	30	robfinch	`wai <= 1'b0;`
45	20	robfinch	`if (im) begin`
46	32	robfinch	`if (ttrig) begin`
47			ir[7:0] <= `BRK;
48			`vect <= {vbr[31:9],9'd490,2'b00};`
49	35	robfinch	`next_state(DECODE);`
50	32	robfinch	`end`
51			`else if (isExec) begin`
52	25	robfinch	`ir <= exbuf;`
53			`exbuf <= 64'd0;`
54			`suppress_pcinc <= 4'h0;`
55	35	robfinch	`next_state(DECODE);`
56	25	robfinch	`end`
57			`else if (unCachedInsn) begin`
58	20	robfinch	`if (bhit) begin`
59	25	robfinch	`ir <= ibuf + exbuf;`
60			`exbuf <= 64'd0;`
61	35	robfinch	`next_state(DECODE);`
62	20	robfinch	`end`
63	35	robfinch	`else begin`
64			`pg2 <= pg2;`
65	32	robfinch	`state <= LOAD_IBUF1;`
66	35	robfinch	`end`
67	20	robfinch	`end`
68			`else begin`
69			`if (ihit) begin`
70	25	robfinch	`ir <= insn + exbuf;`
71			`exbuf <= 64'd0;`
72	35	robfinch	`next_state(DECODE);`
73	20	robfinch	`end`
74	35	robfinch	`else begin`
75			`pg2 <= pg2;`
76	38	robfinch	`next_state(ICACHE1);`
77	35	robfinch	`end`
78	20	robfinch	`end`
79			`end`
80			`else begin`
81	32	robfinch	ir[7:0] <= `BRK;
82	25	robfinch	hwi <= `TRUE;
83	38	robfinch	`if (spi) begin`
84			`spi <= 1'b0;`
85			`spi_cnt <= SPIN_CYCLES;`
86			`vect <= {vbr[31:9],9'd3,2'b00};`
87			`end`
88			`else begin`
89			`vect <= {vbr[31:9],irq_vect,2'b00};`
90			`end`
91	35	robfinch	`next_state(DECODE);`
92	20	robfinch	`end`
93			`end`
94			`else if (!wai) begin`
95	32	robfinch	`if (ttrig) begin`
96			ir[7:0] <= `BRK;
97			`vect <= {vbr[31:9],9'd490,2'b00};`
98	35	robfinch	`next_state(DECODE);`
99	32	robfinch	`end`
100			`else if (isExec) begin`
101	25	robfinch	`ir <= exbuf;`
102			`exbuf <= 64'd0;`
103			`suppress_pcinc <= 4'h0;`
104	35	robfinch	`next_state(DECODE);`
105	25	robfinch	`end`
106			`else if (unCachedInsn) begin`
107	20	robfinch	`if (bhit) begin`
108	25	robfinch	`ir <= ibuf + exbuf;`
109			`exbuf <= 64'd0;`
110	35	robfinch	`next_state(DECODE);`
111	20	robfinch	`end`
112	35	robfinch	`else begin`
113			`pg2 <= pg2;`
114	32	robfinch	`state <= LOAD_IBUF1;`
115	35	robfinch	`end`
116	20	robfinch	`end`
117			`else begin`
118			`if (ihit) begin`
119	25	robfinch	`ir <= insn + exbuf;`
120			`exbuf <= 64'd0;`
121	35	robfinch	`next_state(DECODE);`
122	20	robfinch	`end`
123	35	robfinch	`else begin`
124			`pg2 <= pg2;`
125			`next_state(ICACHE1);`
126			`end`
127	20	robfinch	`end`
128			`end`
129	32	robfinch	`// During a cache miss all these assignments will repeat. It's not a`
130			`// problem. The history buffer will be stuffed with the same pc address`
131			`// for several cycles until the cache load is complete.`
132	35	robfinch	`ifdef DEBUG
133	32	robfinch	`if (hist_capture) begin`
134			`history_buf[history_ndx] <= pc;`
135			`history_ndx <= history_ndx+7'd1;`
136			`end`
137	35	robfinch	`endif
138	32	robfinch	`case(ir9)`
139	35	robfinch	`TAS,`TXS: begin isp <= res[31:0]; gie <= 1'b1; end
140			`SUB_SP8,`SUB_SP16,`SUB_SP32: isp <= res[31:0];
141	32	robfinch	`TRS:
142	30	robfinch	`begin`
143	32	robfinch	`case(ir[15:12])`
144			`4'h0: begin`
145			`$display("res=%h",res);`
146	30	robfinch	`ifdef SUPPORT_ICACHE
147	32	robfinch	`icacheOn <= res[0];`
148	30	robfinch	`endif
149			`ifdef SUPPORT_DCACHE
150	32	robfinch	`dcacheOn <= res[1];`
151			`write_allocate <= res[2];`
152	30	robfinch	`endif
153	32	robfinch	`end`
154	35	robfinch	`4'h5: lfsr <= res[31:0];`
155			`4'h7: abs8 <= res[31:0];`
156	32	robfinch	`4'h8: begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end`
157	38	robfinch	`4'hE: begin sp <= res[15:0]; spage[31:16] <= res[31:16]; end`
158	35	robfinch	`4'hF: begin isp <= res[31:0]; gie <= 1'b1; end`
159	32	robfinch	`endcase`
160			`end`
161			`RR:
162			`case(ir[23:20])`
163			`ADD_RR: begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
164			`SUB_RR:
165	20	robfinch	`if (Rt==4'h0) // CMP doesn't set overflow`
166			`begin cf <= ~resc32; nf <= resn32; zf <= resz32; end`
167			`else`
168			`begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end`
169	32	robfinch	`AND_RR:
170			`if (Rt==4'h0) // BIT sets overflow`
171			`begin nf <= b[31]; vf <= b[30]; zf <= resz32; end`
172			`else`
173	20	robfinch	`begin nf <= resn32; zf <= resz32; end`
174	32	robfinch	`default:`
175			`begin nf <= resn32; zf <= resz32; end`
176			`endcase`
177			`LD_RR: begin zf <= resz32; nf <= resn32; end
178			`DEC_RR,`INC_RR: begin zf <= resz32; nf <= resn32; end
179	38	robfinch	`ADD_IMM4,`ADD_R,
180	32	robfinch	`ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
181			`begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end`
182	38	robfinch	`SUB_IMM4,`SUB_R,
183	32	robfinch	`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
184			`if (Rt==4'h0) // CMP doesn't set overflow`
185			`begin cf <= ~resc32; nf <= resn32; zf <= resz32; end`
186			`else`
187			`begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end`
188			`ifdef SUPPORT_DIVMOD
189			`DIV_IMM8,`DIV_IMM16,`DIV_IMM32,
190			`MOD_IMM8,`MOD_IMM16,`MOD_IMM32,
191			`endif
192			`MUL_IMM8,`MUL_IMM16,`MUL_IMM32:
193			`begin nf <= resn32; zf <= resz32; end`
194	38	robfinch	`AND_IMM4,`AND_R,
195	32	robfinch	`AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:
196			`if (Rt==4'h0) // BIT sets overflow`
197			`begin nf <= b[31]; vf <= b[30]; zf <= resz32; end`
198			`else`
199			`begin nf <= resn32; zf <= resz32; end`
200			`ORB_ZPX,`ORB_ABS,`ORB_ABSX,
201	38	robfinch	`OR_IMM4,`OR_R,
202	32	robfinch	`OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
203	38	robfinch	`EOR_IMM4,`EOR_R,
204	32	robfinch	`EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
205			`begin nf <= resn32; zf <= resz32; end`
206			`ASL_ACC,`ROL_ACC,`LSR_ACC,`ROR_ACC:
207			`begin cf <= resc32; nf <= resn32; zf <= resz32; end`
208			`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,
209			`ASL_ZPX,`ASL_ABS,`ASL_ABSX,
210			`ROL_ZPX,`ROL_ABS,`ROL_ABSX,
211			`LSR_ZPX,`LSR_ABS,`LSR_ABSX,
212			`ROR_ZPX,`ROR_ABS,`ROR_ABSX:
213			`begin cf <= resc32; nf <= resn32; zf <= resz32; end`
214			`ASL_IMM8: begin nf <= resn32; zf <= resz32; end
215			`LSR_IMM8: begin nf <= resn32; zf <= resz32; end
216			`BMT_ZPX,`BMT_ABS,`BMT_ABSX: begin nf <= resn32; zf <= resz32; end
217			`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn32; zf <= resz32; end
218			`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn32; zf <= resz32; end
219			`TAX,`TYX,`TSX,`DEX,`INX,
220			`LDX_IMM32,`LDX_IMM16,`LDX_IMM8,`LDX_ZPY,`LDX_ABS,`LDX_ABSY,`PLX:
221			`begin nf <= resn32; zf <= resz32; end`
222			`TAY,`TXY,`DEY,`INY,
223			`LDY_IMM32,`LDY_ZPX,`LDY_ABS,`LDY_ABSX,`PLY:
224			`begin nf <= resn32; zf <= resz32; end`
225			`CPX_IMM32,`CPX_ZPX,`CPX_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
226			`CPY_IMM32,`CPY_ZPX,`CPY_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
227			`CMP_IMM8: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
228			`TSA,`TYA,`TXA,`INA,`DEA,
229			`LDA_IMM32,`LDA_IMM16,`LDA_IMM8,`PLA: begin nf <= resn32; zf <= resz32; end
230			`POP: begin nf <= resn32; zf <= resz32; end
231	36	robfinch	`TRB_ZPX,`TRB_ABS,`TSB_ZPX,`TSB_ABS:
232			`begin zf <= resz32; end`
233			`BMT_ZPX,`BMT_ABS,`BMT_ABSX:
234			`begin zf <= resz32; nf <= resn32; end`
235	38	robfinch	// `SPL: begin if (radr==65002) acc <= 32'h52544600; end
236	32	robfinch	`endcase`
237	20	robfinch	`end`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [ifetch.v] - Blame information for rev 41