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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_mac.v] - Blame information for rev 38

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013, 2014  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
LOAD_MAC1:
`ifdef SUPPORT_DCACHE
        if (unCachedData)
`endif
        begin
                if (isRMW)
                        lock_o <= 1'b1;
                wb_read({radr,2'b00});
                state <= LOAD_MAC2;
        end
`ifdef SUPPORT_DCACHE
        else if (dhit)
                load_tsk(rdat,rdat8);
        else begin
                retstate <= LOAD_MAC1;
                state <= DCACHE1;
        end
`endif
LOAD_MAC2:
        if (ack_i) begin
                wb_nack();
                load_tsk(dat_i,dati);
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                lock_o <= 1'b0;
                wb_nack();
                if (em | isOrb)
                        derr_address <= adr_o[31:0];
                else
                        derr_address <= adr_o[33:2];
                intno <= 9'd508;
                state <= BUS_ERROR;
        end
`endif
LOAD_MAC3:
        begin
                // Rt will be zero by the time the IFETCH stage is entered because of
                // the decrement below.
                if (Rt==4'd1)
                        state <= IFETCH;
                else begin
                        radr <= isp;
                        isp <= isp_inc;
                        state <= LOAD_MAC1;
                end
                Rt <= Rt - 4'd1;
        end
 
RTS1:
        begin
                pc <= pc + 32'd1;
                state <= BYTE_IFETCH;
        end
IY3:
        begin
                radr <= radr + y;
                wadr <= radr + y;
                if (ir9==`ST_IY) begin
                        store_what <= `STW_A;
                        state <= STORE1;
                end
                else if (ir9==`LEA_IY) begin
                        res <= radr + y;
                        next_state(IFETCH);
                end
                else begin
                        load_what <= `WORD_310;
                        state <= LOAD_MAC1;
                end
                isIY <= 1'b0;
                isIY24 <= `FALSE;
        end
`ifdef SUPPORT_EM8
BYTE_IX5:
        begin
                isI24 <= `FALSE;
                radr <= ia[31:2];
                radr2LSB <= ia[1:0];
                load_what <= m16 ? `HALF_70 : `BYTE_70;
                state <= LOAD_MAC1;
                if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I || ir[7:0]==`STA_IL) begin
                        wadr <= ia[31:2];
                        wadr2LSB <= ia[1:0];
                        store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
                        state <= STORE1;
                end
`ifdef SUPPORT_816
                else if (ir[7:0]==`PEI) begin
                        set_sp();
                        store_what <= `STW_IA158;
                        state <= STORE1;
                end
`endif
        end
BYTE_IY5:
        begin
                isIY <= `FALSE;
                isIY24 <= `FALSE;
                radr <= iapy8[31:2];
                radr2LSB <= iapy8[1:0];
                $display("IY addr: %h", iapy8);
                if (ir[7:0]==`STA_IY || ir[7:0]==`STA_IYL || ir[7:0]==`STA_DSPIY) begin
                        wadr <= iapy8[31:2];
                        wadr2LSB <= iapy8[1:0];
                        store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
                        state <= STORE1;
                end
                else begin
                        load_what <= m16 ? `HALF_70 : `BYTE_70;
                        state <= LOAD_MAC1;
                end
        end
`endif

Line No.	Rev	Author	Line
1	21	robfinch	`// ============================================================================`
2			`// __`
3	38	robfinch	`// \\__/ o\ (C) 2013, 2014 Robert Finch, Stratford`
4	21	robfinch	`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23			`LOAD_MAC1:`
24	30	robfinch	`ifdef SUPPORT_DCACHE
25			`if (unCachedData)`
26			`endif
27			`begin`
28	21	robfinch	`if (isRMW)`
29			`lock_o <= 1'b1;`
30	35	robfinch	`wb_read({radr,2'b00});`
31	21	robfinch	`state <= LOAD_MAC2;`
32			`end`
33	30	robfinch	`ifdef SUPPORT_DCACHE
34	32	robfinch	`else if (dhit)`
35			`load_tsk(rdat,rdat8);`
36			`else begin`
37			`retstate <= LOAD_MAC1;`
38			`state <= DCACHE1;`
39	21	robfinch	`end`
40	30	robfinch	`endif
41	21	robfinch	`LOAD_MAC2:`
42			`if (ack_i) begin`
43	35	robfinch	`wb_nack();`
44	32	robfinch	`load_tsk(dat_i,dati);`
45	21	robfinch	`end`
46	30	robfinch	`ifdef SUPPORT_BERR
47	21	robfinch	`else if (err_i) begin`
48			`lock_o <= 1'b0;`
49	35	robfinch	`wb_nack();`
50			`if (em \| isOrb)`
51			`derr_address <= adr_o[31:0];`
52			`else`
53			`derr_address <= adr_o[33:2];`
54			`intno <= 9'd508;`
55	21	robfinch	`state <= BUS_ERROR;`
56			`end`
57	30	robfinch	`endif
58	32	robfinch	`LOAD_MAC3:`
59			`begin`
60			`// Rt will be zero by the time the IFETCH stage is entered because of`
61			`// the decrement below.`
62			`if (Rt==4'd1)`
63			`state <= IFETCH;`
64			`else begin`
65			`radr <= isp;`
66			`isp <= isp_inc;`
67			`state <= LOAD_MAC1;`
68			`end`
69			`Rt <= Rt - 4'd1;`
70			`end`
71
72	21	robfinch	`RTS1:`
73			`begin`
74			`pc <= pc + 32'd1;`
75	32	robfinch	`state <= BYTE_IFETCH;`
76	21	robfinch	`end`
77			`IY3:`
78			`begin`
79			`radr <= radr + y;`
80			`wadr <= radr + y;`
81	32	robfinch	if (ir9==`ST_IY) begin
82	30	robfinch	store_what <= `STW_A;
83	21	robfinch	`state <= STORE1;`
84	30	robfinch	`end`
85	36	robfinch	else if (ir9==`LEA_IY) begin
86			`res <= radr + y;`
87			`next_state(IFETCH);`
88			`end`
89	21	robfinch	`else begin`
90			load_what <= `WORD_310;
91			`state <= LOAD_MAC1;`
92			`end`
93			`isIY <= 1'b0;`
94	38	robfinch	isIY24 <= `FALSE;
95	21	robfinch	`end`
96	30	robfinch	`ifdef SUPPORT_EM8
97	21	robfinch	`BYTE_IX5:`
98			`begin`
99	38	robfinch	isI24 <= `FALSE;
100	21	robfinch	`radr <= ia[31:2];`
101			`radr2LSB <= ia[1:0];`
102	38	robfinch	load_what <= m16 ? `HALF_70 : `BYTE_70;
103	21	robfinch	`state <= LOAD_MAC1;`
104	38	robfinch	if (ir[7:0]==`STA_IX \|\| ir[7:0]==`STA_I \|\| ir[7:0]==`STA_IL) begin
105	21	robfinch	`wadr <= ia[31:2];`
106			`wadr2LSB <= ia[1:0];`
107	38	robfinch	store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
108	21	robfinch	`state <= STORE1;`
109			`end`
110	38	robfinch	`ifdef SUPPORT_816
111			else if (ir[7:0]==`PEI) begin
112			`set_sp();`
113			store_what <= `STW_IA158;
114			`state <= STORE1;`
115			`end`
116			`endif
117	21	robfinch	`end`
118			`BYTE_IY5:`
119			`begin`
120			isIY <= `FALSE;
121	38	robfinch	isIY24 <= `FALSE;
122	21	robfinch	`radr <= iapy8[31:2];`
123			`radr2LSB <= iapy8[1:0];`
124			`$display("IY addr: %h", iapy8);`
125	38	robfinch	if (ir[7:0]==`STA_IY \|\| ir[7:0]==`STA_IYL \|\| ir[7:0]==`STA_DSPIY) begin
126	21	robfinch	`wadr <= iapy8[31:2];`
127			`wadr2LSB <= iapy8[1:0];`
128	38	robfinch	store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
129	21	robfinch	`state <= STORE1;`
130			`end`
131			`else begin`
132	38	robfinch	load_what <= m16 ? `HALF_70 : `BYTE_70;
133	21	robfinch	`state <= LOAD_MAC1;`
134			`end`
135			`end`
136	30	robfinch	`endif

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_mac.v] - Blame information for rev 38