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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
LOAD_MAC1:
        if (unCachedData) begin
                if (isRMW)
                        lock_o <= 1'b1;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= LOAD_MAC2;
        end
        else if (dhit) begin
                case(load_what)
                `WORD_310:
                                begin
                                        b <= rdat;
                                        b8 <= rdat8;            // for the orb instruction
                                        state <= CALC;
                                end
                `WORD_311:      // For pla/plx/ply/pop
                                        begin
                                                res <= rdat;
                                                state <= IFETCH;
                                        end
                `BYTE_70:
                                begin
                                        b8 <= rdat8;
                                        state <= BYTE_CALC;
                                end
                `BYTE_71:
                                begin
                                        res8 <= rdat8;
                                        state <= IFETCH;
                                end
                `SR_310:
                                begin
                                        cf <= rdat[0];
                                        zf <= rdat[1];
                                        im <= rdat[2];
                                        df <= rdat[3];
                                        bf <= rdat[4];
                                        em <= rdat[29];
                                        vf <= rdat[30];
                                        nf <= rdat[31];
                                        isp <= isp_inc;
                                        radr <= isp_inc;
                                        if (isRTI)
                                                load_what <= `PC_310;
                                        else    // PLP
                                                state <= IFETCH;
                                end
                `SR_70:
                                begin
                                        cf <= rdat8[0];
                                        zf <= rdat8[1];
                                        im <= rdat8[2];
                                        df <= rdat8[3];
                                        bf <= rdat8[4];
                                        vf <= rdat8[6];
                                        nf <= rdat8[7];
                                        if (isRTI) begin
                                                load_what <= `PC_70;
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        else    // PLP
                                                state <= IFETCH;
                                end
                `PC_70:
                                begin
                                        pc[7:0] <= rdat8;
                                        if (isRTI | isRTS | isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        else begin      // JMP (abs)
                                                radr <= radr34p1[33:2];
                                                radr2LSB <= radr34p1[1:0];
                                        end
                                        load_what <= `PC_158;
                                end
                `PC_158:
                                begin
                                        pc[15:8] <= rdat8;
                                        if (isRTI|isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                                load_what <= `PC_2316;
                                        end
                                        else if (isRTS) // rts instruction
                                                state <= RTS1;
                                        else                    // jmp (abs)
                                                state <= IFETCH;
                                end
                `PC_2316:
                                begin
                                        pc[23:16] <= rdat8;
                                        if (isRTI|isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        load_what <= `PC_3124;
                                end
                `PC_3124:
                                begin
                                        pc[31:24] <= rdat8;
                                        load_what <= `NOTHING;
                                        if (isRTL)
                                                state <= RTS1;
                                        else
                                                state <= IFETCH;
                                end
                `PC_310:
                                begin
                                        pc <= rdat;
                                        if (isRTI|isRTS|isRTL)
                                                isp <= isp_inc;
                                        load_what <= `NOTHING;
                                        state <= IFETCH;
                                end
                `IA_310:
                                begin
                                        radr <= rdat;
                                        wadr <= rdat;
                                        wdat <= a;
                                        if (isIY)
                                                state <= IY3;
                                        else if (ir[7:0]==`ST_IX)
                                                state <= STORE1;
                                        else begin
                                                load_what <= `WORD_310;
                                        end
                                end
                `IA_70:
                                begin
                                        radr <= radr34p1[33:2];
                                        radr2LSB <= radr34p1[1:0];
                                        ia[7:0] <= rdat8;
                                        load_what <= `IA_158;
                                end
                `IA_158:
                                begin
                                        ia[15:8] <= rdat8;
                                        ia[31:16] <= 16'h0000;
                                        state <= isIY ? BYTE_IY5 : BYTE_IX5;
                                end
                endcase
        end
        else
                dmiss <= `TRUE;
LOAD_MAC2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                case(load_what)
                `WORD_310:
                                        begin
                                                b <= dat_i;
                                                b8 <= dati;             // for the orb instruction
                                                state <= CALC;
                                        end
                `WORD_311:      // For pla/plx/ply/pop/ldx/ldy
                                        begin
                                                res <= dat_i;
                                                state <= IFETCH;
                                        end
                `BYTE_70:
                                        begin
                                                b8 <= dati;
                                                state <= BYTE_CALC;
                                        end
                `BYTE_71:
                                begin
                                        res8 <= dati;
                                        state <= IFETCH;
                                end
                `SR_310:        begin
                                                cf <= dat_i[0];
                                                zf <= dat_i[1];
                                                im <= dat_i[2];
                                                df <= dat_i[3];
                                                bf <= dat_i[4];
                                                em <= dat_i[29];
                                                vf <= dat_i[30];
                                                nf <= dat_i[31];
                                                isp <= isp_inc;
                                                radr <= isp_inc;
                                                if (isRTI) begin
                                                        load_what <= `PC_310;
                                                        state <= LOAD_MAC1;
                                                end
                                                else    // PLP
                                                        state <= IFETCH;
                                        end
                `SR_70:         begin
                                                cf <= dati[0];
                                                zf <= dati[1];
                                                im <= dati[2];
                                                df <= dati[3];
                                                bf <= dati[4];
                                                vf <= dati[6];
                                                nf <= dati[7];
                                                if (isRTI) begin
                                                        load_what <= `PC_70;
                                                        radr <= {spage[31:8],sp_inc[7:2]};
                                                        radr2LSB <= sp_inc[1:0];
                                                        sp <= sp_inc;
                                                        state <= LOAD_MAC1;
                                                end
                                                else    // PLP
                                                        state <= IFETCH;
                                        end
                `PC_70:         begin
                                                pc[7:0] <= dati;
                                                load_what <= `PC_158;
                                                if (isRTI|isRTS|isRTL) begin
                                                        radr <= {spage[31:8],sp_inc[7:2]};
                                                        radr2LSB <= sp_inc[1:0];
                                                        sp <= sp_inc;
                                                end
                                                else begin      // JMP (abs)
                                                        radr <= radr34p1[33:2];
                                                        radr2LSB <= radr34p1[1:0];
                                                end
                                                state <= LOAD_MAC1;
                                        end
                `PC_158:        begin
                                                pc[15:8] <= dati;
                                                if (isRTI|isRTL) begin
                                                        load_what <= `PC_2316;
                                                        radr <= {spage[31:8],sp_inc[7:2]};
                                                        radr2LSB <= sp_inc[1:0];
                                                        sp <= sp_inc;
                                                        state <= LOAD_MAC1;
                                                end
                                                else if (isRTS) // rts instruction
                                                        state <= RTS1;
                                                else                    // jmp (abs)
                                                        state <= IFETCH;
                                        end
                `PC_2316:       begin
                                                pc[23:16] <= dati;
                                                load_what <= `PC_3124;
                                                if (isRTI|isRTL) begin
                                                        radr <= {spage[31:8],sp_inc[7:2]};
                                                        radr2LSB <= sp_inc[1:0];
                                                        sp <= sp_inc;
                                                end
                                                state <= LOAD_MAC1;
                                        end
                `PC_3124:       begin
                                                pc[31:24] <= dati;
                                                load_what <= `NOTHING;
                                                if (isRTL)
                                                        state <= RTS1;
                                                else
                                                        state <= IFETCH;
                                        end
                `PC_310:        begin
                                                pc <= dat_i;
                                                load_what <= `NOTHING;
                                                if (isRTI | isRTL | isRTS)
                                                        isp <= isp_inc;
                                                state <= IFETCH;
                                        end
                `IA_310:
                                begin
                                        radr <= dat_i;
                                        wadr <= dat_i;
                                        wdat <= a;
                                        if (isIY)
                                                state <= IY3;
                                        else if (ir[7:0]==`ST_IX)
                                                state <= STORE1;
                                        else begin
                                                load_what <= `WORD_310;
                                                state <= LOAD_MAC1;
                                        end
                                end
                `IA_70:
                                begin
                                        radr <= radr34p1[33:2];
                                        radr2LSB <= radr34p1[1:0];
                                        ia[7:0] <= dati;
                                        load_what <= `IA_158;
                                        state <= LOAD_MAC1;
                                end
                `IA_158:
                                begin
                                        ia[15:8] <= dati;
                                        ia[31:16] <= 16'h0000;
                                        state <= isIY ? BYTE_IY5 : BYTE_IX5;
                                end
                endcase
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
RTS1:
        begin
                pc <= pc + 32'd1;
                state <= IFETCH;
        end
IY3:
        begin
                radr <= radr + y;
                wadr <= radr + y;
                wdat <= a;
                if (ir[7:0]==`ST_IY)
                        state <= STORE1;
                else begin
                        load_what <= `WORD_310;
                        state <= LOAD_MAC1;
                end
                isIY <= 1'b0;
        end
BYTE_IX5:
        begin
                radr <= ia[31:2];
                radr2LSB <= ia[1:0];
                load_what <= `BYTE_70;
                state <= LOAD_MAC1;
                if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I) begin
                        wadr <= ia[31:2];
                        wadr2LSB <= ia[1:0];
                        wdat <= {4{acc8}};
                        state <= STORE1;
                end
        end
BYTE_IY5:
        begin
                isIY <= `FALSE;
                radr <= iapy8[31:2];
                radr2LSB <= iapy8[1:0];
                $display("IY addr: %h", iapy8);
                if (ir[7:0]==`STA_IY) begin
                        wadr <= iapy8[31:2];
                        wadr2LSB <= iapy8[1:0];
                        wdat <= {4{acc8}};
                        state <= STORE1;
                end
                else begin
                        load_what <= `BYTE_70;
                        state <= LOAD_MAC1;
                end
        end

Line No.	Rev	Author	Line
1	21	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23			`LOAD_MAC1:`
24			`if (unCachedData) begin`
25			`if (isRMW)`
26			`lock_o <= 1'b1;`
27			`cyc_o <= 1'b1;`
28			`stb_o <= 1'b1;`
29			`sel_o <= 4'hF;`
30			`adr_o <= {radr,2'b00};`
31			`state <= LOAD_MAC2;`
32			`end`
33			`else if (dhit) begin`
34			`case(load_what)`
35			`WORD_310:
36			`begin`
37			`b <= rdat;`
38			`b8 <= rdat8; // for the orb instruction`
39			`state <= CALC;`
40			`end`
41			`WORD_311: // For pla/plx/ply/pop
42			`begin`
43			`res <= rdat;`
44			`state <= IFETCH;`
45			`end`
46			`BYTE_70:
47			`begin`
48			`b8 <= rdat8;`
49			`state <= BYTE_CALC;`
50			`end`
51			`BYTE_71:
52			`begin`
53			`res8 <= rdat8;`
54			`state <= IFETCH;`
55			`end`
56			`SR_310:
57			`begin`
58			`cf <= rdat[0];`
59			`zf <= rdat[1];`
60			`im <= rdat[2];`
61			`df <= rdat[3];`
62			`bf <= rdat[4];`
63			`em <= rdat[29];`
64			`vf <= rdat[30];`
65			`nf <= rdat[31];`
66			`isp <= isp_inc;`
67			`radr <= isp_inc;`
68			`if (isRTI)`
69			load_what <= `PC_310;
70			`else // PLP`
71			`state <= IFETCH;`
72			`end`
73			`SR_70:
74			`begin`
75			`cf <= rdat8[0];`
76			`zf <= rdat8[1];`
77			`im <= rdat8[2];`
78			`df <= rdat8[3];`
79			`bf <= rdat8[4];`
80			`vf <= rdat8[6];`
81			`nf <= rdat8[7];`
82			`if (isRTI) begin`
83			load_what <= `PC_70;
84			`radr <= {spage[31:8],sp_inc[7:2]};`
85			`radr2LSB <= sp_inc[1:0];`
86			`sp <= sp_inc;`
87			`end`
88			`else // PLP`
89			`state <= IFETCH;`
90			`end`
91			`PC_70:
92			`begin`
93			`pc[7:0] <= rdat8;`
94			`if (isRTI \| isRTS \| isRTL) begin`
95			`radr <= {spage[31:8],sp_inc[7:2]};`
96			`radr2LSB <= sp_inc[1:0];`
97			`sp <= sp_inc;`
98			`end`
99			`else begin // JMP (abs)`
100			`radr <= radr34p1[33:2];`
101			`radr2LSB <= radr34p1[1:0];`
102			`end`
103			load_what <= `PC_158;
104			`end`
105			`PC_158:
106			`begin`
107			`pc[15:8] <= rdat8;`
108			`if (isRTI\|isRTL) begin`
109			`radr <= {spage[31:8],sp_inc[7:2]};`
110			`radr2LSB <= sp_inc[1:0];`
111			`sp <= sp_inc;`
112			load_what <= `PC_2316;
113			`end`
114			`else if (isRTS) // rts instruction`
115			`state <= RTS1;`
116			`else // jmp (abs)`
117			`state <= IFETCH;`
118			`end`
119			`PC_2316:
120			`begin`
121			`pc[23:16] <= rdat8;`
122			`if (isRTI\|isRTL) begin`
123			`radr <= {spage[31:8],sp_inc[7:2]};`
124			`radr2LSB <= sp_inc[1:0];`
125			`sp <= sp_inc;`
126			`end`
127			load_what <= `PC_3124;
128			`end`
129			`PC_3124:
130			`begin`
131			`pc[31:24] <= rdat8;`
132			load_what <= `NOTHING;
133			`if (isRTL)`
134			`state <= RTS1;`
135			`else`
136			`state <= IFETCH;`
137			`end`
138			`PC_310:
139			`begin`
140			`pc <= rdat;`
141			`if (isRTI\|isRTS\|isRTL)`
142			`isp <= isp_inc;`
143			load_what <= `NOTHING;
144			`state <= IFETCH;`
145			`end`
146			`IA_310:
147			`begin`
148			`radr <= rdat;`
149			`wadr <= rdat;`
150			`wdat <= a;`
151			`if (isIY)`
152			`state <= IY3;`
153			else if (ir[7:0]==`ST_IX)
154			`state <= STORE1;`
155			`else begin`
156			load_what <= `WORD_310;
157			`end`
158			`end`
159			`IA_70:
160			`begin`
161			`radr <= radr34p1[33:2];`
162			`radr2LSB <= radr34p1[1:0];`
163			`ia[7:0] <= rdat8;`
164			load_what <= `IA_158;
165			`end`
166			`IA_158:
167			`begin`
168			`ia[15:8] <= rdat8;`
169			`ia[31:16] <= 16'h0000;`
170			`state <= isIY ? BYTE_IY5 : BYTE_IX5;`
171			`end`
172			`endcase`
173			`end`
174			`else`
175			dmiss <= `TRUE;
176			`LOAD_MAC2:`
177			`if (ack_i) begin`
178			`cyc_o <= 1'b0;`
179			`stb_o <= 1'b0;`
180			`sel_o <= 4'h0;`
181			`adr_o <= 34'h0;`
182			`case(load_what)`
183			`WORD_310:
184			`begin`
185			`b <= dat_i;`
186			`b8 <= dati; // for the orb instruction`
187			`state <= CALC;`
188			`end`
189			`WORD_311: // For pla/plx/ply/pop/ldx/ldy
190			`begin`
191			`res <= dat_i;`
192			`state <= IFETCH;`
193			`end`
194			`BYTE_70:
195			`begin`
196			`b8 <= dati;`
197			`state <= BYTE_CALC;`
198			`end`
199			`BYTE_71:
200			`begin`
201			`res8 <= dati;`
202			`state <= IFETCH;`
203			`end`
204			`SR_310: begin
205			`cf <= dat_i[0];`
206			`zf <= dat_i[1];`
207			`im <= dat_i[2];`
208			`df <= dat_i[3];`
209			`bf <= dat_i[4];`
210			`em <= dat_i[29];`
211			`vf <= dat_i[30];`
212			`nf <= dat_i[31];`
213			`isp <= isp_inc;`
214			`radr <= isp_inc;`
215			`if (isRTI) begin`
216			load_what <= `PC_310;
217			`state <= LOAD_MAC1;`
218			`end`
219			`else // PLP`
220			`state <= IFETCH;`
221			`end`
222			`SR_70: begin
223			`cf <= dati[0];`
224			`zf <= dati[1];`
225			`im <= dati[2];`
226			`df <= dati[3];`
227			`bf <= dati[4];`
228			`vf <= dati[6];`
229			`nf <= dati[7];`
230			`if (isRTI) begin`
231			load_what <= `PC_70;
232			`radr <= {spage[31:8],sp_inc[7:2]};`
233			`radr2LSB <= sp_inc[1:0];`
234			`sp <= sp_inc;`
235			`state <= LOAD_MAC1;`
236			`end`
237			`else // PLP`
238			`state <= IFETCH;`
239			`end`
240			`PC_70: begin
241			`pc[7:0] <= dati;`
242			load_what <= `PC_158;
243			`if (isRTI\|isRTS\|isRTL) begin`
244			`radr <= {spage[31:8],sp_inc[7:2]};`
245			`radr2LSB <= sp_inc[1:0];`
246			`sp <= sp_inc;`
247			`end`
248			`else begin // JMP (abs)`
249			`radr <= radr34p1[33:2];`
250			`radr2LSB <= radr34p1[1:0];`
251			`end`
252			`state <= LOAD_MAC1;`
253			`end`
254			`PC_158: begin
255			`pc[15:8] <= dati;`
256			`if (isRTI\|isRTL) begin`
257			load_what <= `PC_2316;
258			`radr <= {spage[31:8],sp_inc[7:2]};`
259			`radr2LSB <= sp_inc[1:0];`
260			`sp <= sp_inc;`
261			`state <= LOAD_MAC1;`
262			`end`
263			`else if (isRTS) // rts instruction`
264			`state <= RTS1;`
265			`else // jmp (abs)`
266			`state <= IFETCH;`
267			`end`
268			`PC_2316: begin
269			`pc[23:16] <= dati;`
270			load_what <= `PC_3124;
271			`if (isRTI\|isRTL) begin`
272			`radr <= {spage[31:8],sp_inc[7:2]};`
273			`radr2LSB <= sp_inc[1:0];`
274			`sp <= sp_inc;`
275			`end`
276			`state <= LOAD_MAC1;`
277			`end`
278			`PC_3124: begin
279			`pc[31:24] <= dati;`
280			load_what <= `NOTHING;
281			`if (isRTL)`
282			`state <= RTS1;`
283			`else`
284			`state <= IFETCH;`
285			`end`
286			`PC_310: begin
287			`pc <= dat_i;`
288			load_what <= `NOTHING;
289			`if (isRTI \| isRTL \| isRTS)`
290			`isp <= isp_inc;`
291			`state <= IFETCH;`
292			`end`
293			`IA_310:
294			`begin`
295			`radr <= dat_i;`
296			`wadr <= dat_i;`
297			`wdat <= a;`
298			`if (isIY)`
299			`state <= IY3;`
300			else if (ir[7:0]==`ST_IX)
301			`state <= STORE1;`
302			`else begin`
303			load_what <= `WORD_310;
304			`state <= LOAD_MAC1;`
305			`end`
306			`end`
307			`IA_70:
308			`begin`
309			`radr <= radr34p1[33:2];`
310			`radr2LSB <= radr34p1[1:0];`
311	22	robfinch	`ia[7:0] <= dati;`
312	21	robfinch	load_what <= `IA_158;
313			`state <= LOAD_MAC1;`
314			`end`
315			`IA_158:
316			`begin`
317	22	robfinch	`ia[15:8] <= dati;`
318	21	robfinch	`ia[31:16] <= 16'h0000;`
319			`state <= isIY ? BYTE_IY5 : BYTE_IX5;`
320			`end`
321			`endcase`
322			`end`
323			`else if (err_i) begin`
324			`lock_o <= 1'b0;`
325			`cyc_o <= 1'b0;`
326			`stb_o <= 1'b0;`
327			`we_o <= 1'b0;`
328			`sel_o <= 4'h0;`
329			`adr_o <= 34'h0;`
330			`dat_o <= 32'h0;`
331			`state <= BUS_ERROR;`
332			`end`
333			`RTS1:`
334			`begin`
335			`pc <= pc + 32'd1;`
336			`state <= IFETCH;`
337			`end`
338			`IY3:`
339			`begin`
340			`radr <= radr + y;`
341			`wadr <= radr + y;`
342			`wdat <= a;`
343			if (ir[7:0]==`ST_IY)
344			`state <= STORE1;`
345			`else begin`
346			load_what <= `WORD_310;
347			`state <= LOAD_MAC1;`
348			`end`
349			`isIY <= 1'b0;`
350			`end`
351			`BYTE_IX5:`
352			`begin`
353			`radr <= ia[31:2];`
354			`radr2LSB <= ia[1:0];`
355			load_what <= `BYTE_70;
356			`state <= LOAD_MAC1;`
357			if (ir[7:0]==`STA_IX \|\| ir[7:0]==`STA_I) begin
358			`wadr <= ia[31:2];`
359			`wadr2LSB <= ia[1:0];`
360			`wdat <= {4{acc8}};`
361			`state <= STORE1;`
362			`end`
363			`end`
364			`BYTE_IY5:`
365			`begin`
366			isIY <= `FALSE;
367			`radr <= iapy8[31:2];`
368			`radr2LSB <= iapy8[1:0];`
369			`$display("IY addr: %h", iapy8);`
370			if (ir[7:0]==`STA_IY) begin
371			`wadr <= iapy8[31:2];`
372			`wadr2LSB <= iapy8[1:0];`
373			`wdat <= {4{acc8}};`
374			`state <= STORE1;`
375			`end`
376			`else begin`
377			load_what <= `BYTE_70;
378			`state <= LOAD_MAC1;`
379			`end`
380			`end`

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