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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_mac.v] - Blame information for rev 36

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2013  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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LOAD_MAC1:
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`ifdef SUPPORT_DCACHE
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        if (unCachedData)
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`endif
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        begin
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                if (isRMW)
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                        lock_o <= 1'b1;
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                wb_read({radr,2'b00});
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                state <= LOAD_MAC2;
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        end
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`ifdef SUPPORT_DCACHE
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        else if (dhit)
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                load_tsk(rdat,rdat8);
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        else begin
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                retstate <= LOAD_MAC1;
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                state <= DCACHE1;
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        end
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`endif
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LOAD_MAC2:
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        if (ack_i) begin
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                wb_nack();
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                load_tsk(dat_i,dati);
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        end
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`ifdef SUPPORT_BERR
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        else if (err_i) begin
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                lock_o <= 1'b0;
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                wb_nack();
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                if (em | isOrb)
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                        derr_address <= adr_o[31:0];
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                else
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                        derr_address <= adr_o[33:2];
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                intno <= 9'd508;
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                state <= BUS_ERROR;
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        end
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`endif
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LOAD_MAC3:
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        begin
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                // Rt will be zero by the time the IFETCH stage is entered because of
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                // the decrement below.
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                if (Rt==4'd1)
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                        state <= IFETCH;
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                else begin
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                        radr <= isp;
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                        isp <= isp_inc;
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                        state <= LOAD_MAC1;
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                end
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                Rt <= Rt - 4'd1;
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        end
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RTS1:
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        begin
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                pc <= pc + 32'd1;
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                state <= BYTE_IFETCH;
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        end
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IY3:
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        begin
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                radr <= radr + y;
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                wadr <= radr + y;
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                if (ir9==`ST_IY) begin
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                        store_what <= `STW_A;
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                        state <= STORE1;
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                end
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                else if (ir9==`LEA_IY) begin
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                        res <= radr + y;
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                        next_state(IFETCH);
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                end
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                else begin
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                        load_what <= `WORD_310;
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                        state <= LOAD_MAC1;
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                end
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                isIY <= 1'b0;
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        end
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`ifdef SUPPORT_EM8
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BYTE_IX5:
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        begin
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                radr <= ia[31:2];
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                radr2LSB <= ia[1:0];
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                load_what <= `BYTE_70;
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                state <= LOAD_MAC1;
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                if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I) begin
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                        wadr <= ia[31:2];
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                        wadr2LSB <= ia[1:0];
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                        store_what <= `STW_ACC8;
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                        state <= STORE1;
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                end
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        end
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BYTE_IY5:
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        begin
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                isIY <= `FALSE;
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                radr <= iapy8[31:2];
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                radr2LSB <= iapy8[1:0];
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                $display("IY addr: %h", iapy8);
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                if (ir[7:0]==`STA_IY) begin
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                        wadr <= iapy8[31:2];
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                        wadr2LSB <= iapy8[1:0];
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                        store_what <= `STW_ACC8;
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                        state <= STORE1;
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                end
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                else begin
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                        load_what <= `BYTE_70;
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                        state <= LOAD_MAC1;
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                end
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        end
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`endif

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