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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_tsk.v] - Blame information for rev 36

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
task load_tsk;
input [31:0] dat;
input [7:0] dat8;
begin
        case(load_what)
        `WORD_310:
                                begin
                                        b <= dat;
                                        b8 <= dat8;             // for the orb instruction
                                        state <= CALC;
                                end
        `WORD_311:      // For pla/plx/ply/pop/ldx/ldy
                                begin
                                        if (ir9==`POP)
                                                Rt <= ir[15:12];
                                        res <= dat;
                                        state <= isPopa ? LOAD_MAC3 : IFETCH;
                                end
        `WORD_312:
                        begin
                                b <= dat;
                                radr <= y;
                                wadr <= y;
                                store_what <= `STW_B;
                                x <= res[31:0];
                                acc <= acc - 32'd1;
                                state <= STORE1;
                        end
        `WORD_313:
                        begin
                                a <= dat;
                                radr <= y;
                                load_what <= `WORD_314;
                                x <= res[31:0];
                                state <= LOAD_MAC1;
                        end
        `WORD_314:
                        begin
                                b <= dat;
                                acc <= acc - 32'd1;
                                state <= CMPS1;
                        end
`ifdef SUPPORT_EM8
        `BYTE_70:
                                begin
                                        b8 <= dat8;
                                        state <= BYTE_CALC;
                                end
        `BYTE_71:
                        begin
                                res8 <= dat8;
                                state <= BYTE_IFETCH;
                        end
`endif
        `SR_310:        begin
                                        cf <= dat[0];
                                        zf <= dat[1];
                                        im <= dat[2];
                                        df <= dat[3];
                                        bf <= dat[4];
                                        tf <= dat[28];
                                        em <= dat[29];
                                        vf <= dat[30];
                                        nf <= dat[31];
                                        if (isRTI) begin
                                                radr <= isp;
                                                isp <= isp_inc;
                                                load_what <= `PC_310;
                                                state <= LOAD_MAC1;
                                        end
                                        else    // PLP
                                                state <= IFETCH;
                                end
`ifdef SUPPORT_EM8
        `SR_70:         begin
                                        cf <= dat8[0];
                                        zf <= dat8[1];
                                        im <= dat8[2];
                                        df <= dat8[3];
                                        bf <= dat8[4];
                                        vf <= dat8[6];
                                        nf <= dat8[7];
                                        if (isRTI) begin
                                                load_what <= `PC_70;
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                                state <= LOAD_MAC1;
                                        end
                                        else    // PLP
                                                state <= BYTE_IFETCH;
                                end
        `PC_70:         begin
                                        pc[7:0] <= dat8;
                                        load_what <= `PC_158;
                                        if (isRTI|isRTS|isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        else begin      // JMP (abs)
                                                radr <= radr34p1[33:2];
                                                radr2LSB <= radr34p1[1:0];
                                        end
                                        state <= LOAD_MAC1;
                                end
        `PC_158:        begin
                                        pc[15:8] <= dat8;
                                        if (isRTI|isRTL) begin
                                                load_what <= `PC_2316;
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                                state <= LOAD_MAC1;
                                        end
                                        else if (isRTS) // rts instruction
                                                state <= RTS1;
                                        else                    // jmp (abs)
                                                state <= BYTE_IFETCH;
                                end
        `PC_2316:       begin
                                        pc[23:16] <= dat8;
                                        load_what <= `PC_3124;
                                        if (isRTI|isRTL) begin
                                                radr <= {spage[31:8],sp_inc[7:2]};
                                                radr2LSB <= sp_inc[1:0];
                                                sp <= sp_inc;
                                        end
                                        state <= LOAD_MAC1;
                                end
        `PC_3124:       begin
                                        pc[31:24] <= dat8;
                                        load_what <= `NOTHING;
                                        if (isRTL)
                                                state <= RTS1;
                                        else
                                                state <= BYTE_IFETCH;
                                end
`endif
        `PC_310:        begin
                                        pc <= dat;
                                        load_what <= `NOTHING;
                                        if (isRTI) begin
                                                km <= `FALSE;
`ifdef DEBUG
                                                hist_capture <= `TRUE;
`endif
                                        end
                                        state <= em ? BYTE_IFETCH : IFETCH;
                                end
        `IA_310:
                        begin
                                radr <= dat;
                                wadr <= dat;
                                wdat <= a;
                                if (isIY)
                                        state <= IY3;
                                else if (ir9==`ST_IX)
                                        state <= STORE1;
                                else if (ir9==`LEA_IX) begin
                                        res <= dat;
                                        next_state(IFETCH);
                                end
                                else begin
                                        load_what <= `WORD_310;
                                        state <= LOAD_MAC1;
                                end
                        end
`ifdef SUPPORT_EM8
        `IA_70:
                        begin
                                radr <= radr34p1[33:2];
                                radr2LSB <= radr34p1[1:0];
                                ia[7:0] <= dat8;
                                load_what <= `IA_158;
                                state <= LOAD_MAC1;
                        end
        `IA_158:
                        begin
                                ia[15:8] <= dat8;
                                ia[31:16] <= abs8[31:16];
                                state <= isIY ? BYTE_IY5 : BYTE_IX5;
                        end
`endif
        endcase
end
endtask

Line No.	Rev	Author	Line
1	32	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23			`task load_tsk;`
24			`input [31:0] dat;`
25			`input [7:0] dat8;`
26			`begin`
27			`case(load_what)`
28			`WORD_310:
29			`begin`
30			`b <= dat;`
31			`b8 <= dat8; // for the orb instruction`
32			`state <= CALC;`
33			`end`
34			`WORD_311: // For pla/plx/ply/pop/ldx/ldy
35			`begin`
36	36	robfinch	if (ir9==`POP)
37			`Rt <= ir[15:12];`
38	32	robfinch	`res <= dat;`
39			`state <= isPopa ? LOAD_MAC3 : IFETCH;`
40			`end`
41			`WORD_312:
42			`begin`
43			`b <= dat;`
44			`radr <= y;`
45			`wadr <= y;`
46			store_what <= `STW_B;
47	35	robfinch	`x <= res[31:0];`
48	32	robfinch	`acc <= acc - 32'd1;`
49			`state <= STORE1;`
50			`end`
51			`WORD_313:
52			`begin`
53			`a <= dat;`
54			`radr <= y;`
55			load_what <= `WORD_314;
56	35	robfinch	`x <= res[31:0];`
57	32	robfinch	`state <= LOAD_MAC1;`
58			`end`
59			`WORD_314:
60			`begin`
61			`b <= dat;`
62			`acc <= acc - 32'd1;`
63			`state <= CMPS1;`
64			`end`
65			`ifdef SUPPORT_EM8
66			`BYTE_70:
67			`begin`
68			`b8 <= dat8;`
69			`state <= BYTE_CALC;`
70			`end`
71			`BYTE_71:
72			`begin`
73			`res8 <= dat8;`
74			`state <= BYTE_IFETCH;`
75			`end`
76			`endif
77			`SR_310: begin
78			`cf <= dat[0];`
79			`zf <= dat[1];`
80			`im <= dat[2];`
81			`df <= dat[3];`
82			`bf <= dat[4];`
83			`tf <= dat[28];`
84			`em <= dat[29];`
85			`vf <= dat[30];`
86			`nf <= dat[31];`
87			`if (isRTI) begin`
88			`radr <= isp;`
89			`isp <= isp_inc;`
90			load_what <= `PC_310;
91			`state <= LOAD_MAC1;`
92			`end`
93			`else // PLP`
94			`state <= IFETCH;`
95			`end`
96			`ifdef SUPPORT_EM8
97			`SR_70: begin
98			`cf <= dat8[0];`
99			`zf <= dat8[1];`
100			`im <= dat8[2];`
101			`df <= dat8[3];`
102			`bf <= dat8[4];`
103			`vf <= dat8[6];`
104			`nf <= dat8[7];`
105			`if (isRTI) begin`
106			load_what <= `PC_70;
107			`radr <= {spage[31:8],sp_inc[7:2]};`
108			`radr2LSB <= sp_inc[1:0];`
109			`sp <= sp_inc;`
110			`state <= LOAD_MAC1;`
111			`end`
112			`else // PLP`
113			`state <= BYTE_IFETCH;`
114			`end`
115			`PC_70: begin
116			`pc[7:0] <= dat8;`
117			load_what <= `PC_158;
118			`if (isRTI\|isRTS\|isRTL) begin`
119			`radr <= {spage[31:8],sp_inc[7:2]};`
120			`radr2LSB <= sp_inc[1:0];`
121			`sp <= sp_inc;`
122			`end`
123			`else begin // JMP (abs)`
124			`radr <= radr34p1[33:2];`
125			`radr2LSB <= radr34p1[1:0];`
126			`end`
127			`state <= LOAD_MAC1;`
128			`end`
129			`PC_158: begin
130			`pc[15:8] <= dat8;`
131			`if (isRTI\|isRTL) begin`
132			load_what <= `PC_2316;
133			`radr <= {spage[31:8],sp_inc[7:2]};`
134			`radr2LSB <= sp_inc[1:0];`
135			`sp <= sp_inc;`
136			`state <= LOAD_MAC1;`
137			`end`
138			`else if (isRTS) // rts instruction`
139			`state <= RTS1;`
140			`else // jmp (abs)`
141			`state <= BYTE_IFETCH;`
142			`end`
143			`PC_2316: begin
144			`pc[23:16] <= dat8;`
145			load_what <= `PC_3124;
146			`if (isRTI\|isRTL) begin`
147			`radr <= {spage[31:8],sp_inc[7:2]};`
148			`radr2LSB <= sp_inc[1:0];`
149			`sp <= sp_inc;`
150			`end`
151			`state <= LOAD_MAC1;`
152			`end`
153			`PC_3124: begin
154			`pc[31:24] <= dat8;`
155			load_what <= `NOTHING;
156			`if (isRTL)`
157			`state <= RTS1;`
158			`else`
159			`state <= BYTE_IFETCH;`
160			`end`
161			`endif
162			`PC_310: begin
163			`pc <= dat;`
164			load_what <= `NOTHING;
165			`if (isRTI) begin`
166			km <= `FALSE;
167	35	robfinch	`ifdef DEBUG
168	32	robfinch	hist_capture <= `TRUE;
169	35	robfinch	`endif
170	32	robfinch	`end`
171			`state <= em ? BYTE_IFETCH : IFETCH;`
172			`end`
173			`IA_310:
174			`begin`
175			`radr <= dat;`
176			`wadr <= dat;`
177			`wdat <= a;`
178			`if (isIY)`
179			`state <= IY3;`
180			else if (ir9==`ST_IX)
181			`state <= STORE1;`
182	36	robfinch	else if (ir9==`LEA_IX) begin
183			`res <= dat;`
184			`next_state(IFETCH);`
185			`end`
186	32	robfinch	`else begin`
187			load_what <= `WORD_310;
188			`state <= LOAD_MAC1;`
189			`end`
190			`end`
191			`ifdef SUPPORT_EM8
192			`IA_70:
193			`begin`
194			`radr <= radr34p1[33:2];`
195			`radr2LSB <= radr34p1[1:0];`
196			`ia[7:0] <= dat8;`
197			load_what <= `IA_158;
198			`state <= LOAD_MAC1;`
199			`end`
200			`IA_158:
201			`begin`
202			`ia[15:8] <= dat8;`
203			`ia[31:16] <= abs8[31:16];`
204			`state <= isIY ? BYTE_IY5 : BYTE_IX5;`
205			`end`
206			`endif
207			`endcase`
208			`end`
209			`endtask`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_tsk.v] - Blame information for rev 36