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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_tsk.v] - Blame information for rev 39

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013,2014  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
task load_tsk;
input [31:0] dat;
input [7:0] dat8;
begin
        case(load_what)
        `WORD_310:
                                begin
                                        b <= dat;
                                        b8 <= dat8;             // for the orb instruction
                                        state <= CALC;
                                end
        `WORD_311:      // For pla/plx/ply/pop/ldx/ldy
                                begin
                                        if (ir9==`POP)
                                                Rt <= ir[15:12];
                                        res <= dat;
                                        state <= isPopa ? LOAD_MAC3 : IFETCH;
                                end
        `WORD_312:
                        begin
                                b <= dat;
                                radr <= y;
                                wadr <= y;
                                store_what <= `STW_B;
                                x <= res[31:0];
                                acc <= acc_dec;
                                state <= STORE1;
                        end
        `WORD_313:
                        begin
                                a <= dat;
                                radr <= y;
                                load_what <= `WORD_314;
                                x <= res[31:0];
                                state <= LOAD_MAC1;
                        end
        `WORD_314:
                        begin
                                b <= dat;
                                acc <= acc - 32'd1;
                                state <= CMPS1;
                        end
`ifdef SUPPORT_EM8
        `BYTE_70:
                                begin
                                        b8 <= dat8;
                                        state <= BYTE_CALC;
                                end
        `BYTE_71:
                        begin
                                res8 <= dat8;
                                state <= BYTE_IFETCH;
                        end
`endif
`ifdef SUPPORT_816
        `HALF_70:
                                begin
                                        b16[7:0] <= dat8;
                                        load_what <= `HALF_158;
                                        if (radr2LSB==2'b11)
                                                radr <= radr+32'd1;
                                        radr2LSB <= radr2LSB + 2'b01;
                                        state <= LOAD_MAC1;
                                end
        `HALF_158:
                                begin
                                        b16[15:8] <= dat8;
                                        state <= HALF_CALC;
                                end
        `HALF_71:
                                begin
                                        res16[7:0] <= dat8;
                                        load_what <= `HALF_159;
                                        if (radr2LSB==2'b11)
                                                radr <= radr+32'd1;
                                        radr2LSB <= radr2LSB + 2'b01;
                                        next_state(LOAD_MAC1);
                                end
        `HALF_159:
                                begin
                                        res16[15:8] <= dat8;
                                        next_state(BYTE_IFETCH);
                                end
        `HALF_71S:
                                begin
                                        res16[7:0] <= dat8;
                                        load_what <= `HALF_159S;
                                        inc_sp();
                                        next_state(LOAD_MAC1);
                                end
        `HALF_159S:
                                begin
                                        res16[15:8] <= dat8;
                                        next_state(BYTE_IFETCH);
                                end
        `BYTE_72:
                                begin
                                        wdat[7:0] <= dat8;
                                        radr <= mvndst_address[31:2];
                                        radr2LSB <= mvndst_address[1:0];
                                        wadr <= mvndst_address[31:2];
                                        wadr2LSB <= mvndst_address[1:0];
                                        store_what <= `STW_DEF8;
                                        acc[15:0] <= acc_dec[15:0];
                                        if (ir9==`MVN) begin
                                                x[15:0] <= x_inc[15:0];
                                                y[15:0] <= y_inc[15:0];
                                        end
                                        else begin
                                                x[15:0] <= x_dec[15:0];
                                                y[15:0] <= y_dec[15:0];
                                        end
                                        next_state(STORE1);
                                end
`endif
        `SR_310:        begin
                                        cf <= dat[0];
                                        zf <= dat[1];
                                        im <= dat[2];
                                        df <= dat[3];
                                        bf <= dat[4];
                                        x_bit <= dat[8];
                                        m_bit <= dat[9];
                                        m816 <= dat[10];
                                        tf <= dat[28];
                                        em <= dat[29];
                                        vf <= dat[30];
                                        nf <= dat[31];
                                        if (isRTI) begin
                                                // If we will be returning to emulation mode and emulating the 816
                                                // then force the upper part of the registers to zero if eigth bit
                                                // registers are selected.
//                                              if (dat[10] & dat[29]) begin
//                                                      if (dat[8]) begin
//                                                              x[31:8] <= 24'd0;
//                                                              y[31:8] <= 24'd0;
//                                                      end
//                                                      //if (dat[9]) acc[31:8] <= 24'd0;
//                                              end
                                                radr <= isp;
                                                isp <= isp_inc;
                                                load_what <= `PC_310;
                                                state <= LOAD_MAC1;
                                        end
                                        else    // PLP
                                                state <= IFETCH;
                                end
`ifdef SUPPORT_EM8
        `SR_70:         begin
                                        cf <= dat8[0];
                                        zf <= dat8[1];
                                        im <= dat8[2];
                                        df <= dat8[3];
                                        if (m816) begin
                                                x_bit <= dat8[4];
                                                m_bit <= dat8[5];
                                                if (dat8[4]) begin
                                                        x[31:8] <= 24'd0;
                                                        y[31:8] <= 24'd0;
                                                end
                                                //if (dat8[5]) acc[31:8] <= 24'd0;
                                        end
                                        else
                                                bf <= dat8[4];
                                        vf <= dat8[6];
                                        nf <= dat8[7];
                                        if (isRTI) begin
                                                load_what <= `PC_70;
                                                inc_sp();
                                                state <= LOAD_MAC1;
                                        end
                                        else    // PLP
                                                state <= BYTE_IFETCH;
                                end
        `PC_70:         begin
                                        pc[7:0] <= dat8;
                                        load_what <= `PC_158;
                                        if (isRTI|isRTS|isRTL) begin
                                                inc_sp();
                                        end
                                        else begin      // JMP (abs)
                                                radr <= radr34p1[33:2];
                                                radr2LSB <= radr34p1[1:0];
                                        end
                                        state <= LOAD_MAC1;
                                end
        `PC_158:        begin
                                        pc[15:8] <= dat8;
                                        if ((isRTI&m816)|isRTL) begin
                                                load_what <= `PC_2316;
                                                inc_sp();
                                                state <= LOAD_MAC1;
                                        end
                                        else if (isRTS) // rts instruction
                                                next_state(RTS1);
                                        else                    // jmp (abs)
                                                next_state(BYTE_IFETCH);
                                end
        `PC_2316:       begin
                                        pc[23:16] <= dat8;
                                        if (isRTL) begin
                                                load_what <= `NOTHING;
                                                next_state(RTS1);
                                        end
                                        else begin
                                                load_what <= `NOTHING;
                                                next_state(BYTE_IFETCH);
//                                              load_what <= `PC_3124;
//                                              if (isRTI) begin
//                                                      inc_sp();
//                                              end
//                                              state <= LOAD_MAC1;     
                                        end
                                end
        `PC_3124:       begin
                                        pc[31:24] <= dat8;
                                        load_what <= `NOTHING;
                                        next_state(BYTE_IFETCH);
                                end
`endif
        `PC_310:        begin
                                        pc <= dat;
                                        load_what <= `NOTHING;
                                        if (isRTI) begin
                                                km <= `FALSE;
`ifdef DEBUG
                                                hist_capture <= `TRUE;
`endif
                                        end
                                        next_state(em ? BYTE_IFETCH : IFETCH);
//                                      else    // indirect jumps
//                                              next_state(IFETCH);
                                end
        `IA_310:
                        begin
                                radr <= dat;
                                wadr <= dat;
                                wdat <= a;
                                if (isIY)
                                        state <= IY3;
                                else if (ir9==`ST_IX)
                                        state <= STORE1;
                                else if (ir9==`LEA_IX) begin
                                        res <= dat;
                                        next_state(IFETCH);
                                end
                                else begin
                                        load_what <= `WORD_310;
                                        state <= LOAD_MAC1;
                                end
                        end
`ifdef SUPPORT_EM8
        `IA_70:
                        begin
                                radr <= radr34p1[33:2];
                                radr2LSB <= radr34p1[1:0];
                                ia[7:0] <= dat8;
                                load_what <= `IA_158;
                                state <= LOAD_MAC1;
                        end
        `IA_158:
                        begin
                                ia[15:8] <= dat8;
                                ia[31:16] <= {abs8[31:24],dbr};
                                if (isIY24|isI24) begin
                                        radr <= radr34p1[33:2];
                                        radr2LSB <= radr34p1[1:0];
                                        load_what <= `IA_2316;
                                        state <= LOAD_MAC1;
                                end
                                else
                                        state <= isIY ? BYTE_IY5 : BYTE_IX5;
                        end
        `IA_2316:
                        begin
                                ia[23:16] <= dat8;
                                ia[31:24] <= abs8[31:24];
                                state <= isIY24 ? BYTE_IY5 : BYTE_IX5;
                        end
`endif
        endcase
end
endtask

Line No.	Rev	Author	Line
1	32	robfinch	`// ============================================================================`
2			`// __`
3	38	robfinch	`// \\__/ o\ (C) 2013,2014 Robert Finch, Stratford`
4	32	robfinch	`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23			`task load_tsk;`
24			`input [31:0] dat;`
25			`input [7:0] dat8;`
26			`begin`
27			`case(load_what)`
28			`WORD_310:
29			`begin`
30			`b <= dat;`
31			`b8 <= dat8; // for the orb instruction`
32			`state <= CALC;`
33			`end`
34			`WORD_311: // For pla/plx/ply/pop/ldx/ldy
35			`begin`
36	36	robfinch	if (ir9==`POP)
37			`Rt <= ir[15:12];`
38	32	robfinch	`res <= dat;`
39			`state <= isPopa ? LOAD_MAC3 : IFETCH;`
40			`end`
41			`WORD_312:
42			`begin`
43			`b <= dat;`
44			`radr <= y;`
45			`wadr <= y;`
46			store_what <= `STW_B;
47	35	robfinch	`x <= res[31:0];`
48	38	robfinch	`acc <= acc_dec;`
49	32	robfinch	`state <= STORE1;`
50			`end`
51			`WORD_313:
52			`begin`
53			`a <= dat;`
54			`radr <= y;`
55			load_what <= `WORD_314;
56	35	robfinch	`x <= res[31:0];`
57	32	robfinch	`state <= LOAD_MAC1;`
58			`end`
59			`WORD_314:
60			`begin`
61			`b <= dat;`
62			`acc <= acc - 32'd1;`
63			`state <= CMPS1;`
64			`end`
65			`ifdef SUPPORT_EM8
66			`BYTE_70:
67			`begin`
68			`b8 <= dat8;`
69			`state <= BYTE_CALC;`
70			`end`
71			`BYTE_71:
72			`begin`
73			`res8 <= dat8;`
74			`state <= BYTE_IFETCH;`
75			`end`
76			`endif
77	38	robfinch	`ifdef SUPPORT_816
78			`HALF_70:
79			`begin`
80			`b16[7:0] <= dat8;`
81			load_what <= `HALF_158;
82			`if (radr2LSB==2'b11)`
83			`radr <= radr+32'd1;`
84			`radr2LSB <= radr2LSB + 2'b01;`
85			`state <= LOAD_MAC1;`
86			`end`
87			`HALF_158:
88			`begin`
89			`b16[15:8] <= dat8;`
90			`state <= HALF_CALC;`
91			`end`
92			`HALF_71:
93			`begin`
94			`res16[7:0] <= dat8;`
95			load_what <= `HALF_159;
96			`if (radr2LSB==2'b11)`
97			`radr <= radr+32'd1;`
98			`radr2LSB <= radr2LSB + 2'b01;`
99			`next_state(LOAD_MAC1);`
100			`end`
101			`HALF_159:
102			`begin`
103			`res16[15:8] <= dat8;`
104			`next_state(BYTE_IFETCH);`
105			`end`
106			`HALF_71S:
107			`begin`
108			`res16[7:0] <= dat8;`
109			load_what <= `HALF_159S;
110			`inc_sp();`
111			`next_state(LOAD_MAC1);`
112			`end`
113			`HALF_159S:
114			`begin`
115			`res16[15:8] <= dat8;`
116			`next_state(BYTE_IFETCH);`
117			`end`
118			`BYTE_72:
119			`begin`
120			`wdat[7:0] <= dat8;`
121			`radr <= mvndst_address[31:2];`
122			`radr2LSB <= mvndst_address[1:0];`
123			`wadr <= mvndst_address[31:2];`
124			`wadr2LSB <= mvndst_address[1:0];`
125			store_what <= `STW_DEF8;
126			`acc[15:0] <= acc_dec[15:0];`
127			if (ir9==`MVN) begin
128			`x[15:0] <= x_inc[15:0];`
129			`y[15:0] <= y_inc[15:0];`
130			`end`
131			`else begin`
132			`x[15:0] <= x_dec[15:0];`
133			`y[15:0] <= y_dec[15:0];`
134			`end`
135			`next_state(STORE1);`
136			`end`
137			`endif
138	32	robfinch	`SR_310: begin
139			`cf <= dat[0];`
140			`zf <= dat[1];`
141			`im <= dat[2];`
142			`df <= dat[3];`
143			`bf <= dat[4];`
144	38	robfinch	`x_bit <= dat[8];`
145			`m_bit <= dat[9];`
146			`m816 <= dat[10];`
147	32	robfinch	`tf <= dat[28];`
148			`em <= dat[29];`
149			`vf <= dat[30];`
150			`nf <= dat[31];`
151			`if (isRTI) begin`
152	38	robfinch	`// If we will be returning to emulation mode and emulating the 816`
153			`// then force the upper part of the registers to zero if eigth bit`
154			`// registers are selected.`
155			`// if (dat[10] & dat[29]) begin`
156			`// if (dat[8]) begin`
157			`// x[31:8] <= 24'd0;`
158			`// y[31:8] <= 24'd0;`
159			`// end`
160			`// //if (dat[9]) acc[31:8] <= 24'd0;`
161			`// end`
162	32	robfinch	`radr <= isp;`
163			`isp <= isp_inc;`
164			load_what <= `PC_310;
165			`state <= LOAD_MAC1;`
166			`end`
167			`else // PLP`
168			`state <= IFETCH;`
169			`end`
170			`ifdef SUPPORT_EM8
171			`SR_70: begin
172			`cf <= dat8[0];`
173			`zf <= dat8[1];`
174			`im <= dat8[2];`
175			`df <= dat8[3];`
176	38	robfinch	`if (m816) begin`
177			`x_bit <= dat8[4];`
178			`m_bit <= dat8[5];`
179			`if (dat8[4]) begin`
180			`x[31:8] <= 24'd0;`
181			`y[31:8] <= 24'd0;`
182			`end`
183			`//if (dat8[5]) acc[31:8] <= 24'd0;`
184			`end`
185			`else`
186			`bf <= dat8[4];`
187	32	robfinch	`vf <= dat8[6];`
188			`nf <= dat8[7];`
189			`if (isRTI) begin`
190			load_what <= `PC_70;
191	38	robfinch	`inc_sp();`
192	32	robfinch	`state <= LOAD_MAC1;`
193			`end`
194			`else // PLP`
195			`state <= BYTE_IFETCH;`
196			`end`
197			`PC_70: begin
198			`pc[7:0] <= dat8;`
199			load_what <= `PC_158;
200			`if (isRTI\|isRTS\|isRTL) begin`
201	38	robfinch	`inc_sp();`
202	32	robfinch	`end`
203			`else begin // JMP (abs)`
204			`radr <= radr34p1[33:2];`
205			`radr2LSB <= radr34p1[1:0];`
206			`end`
207			`state <= LOAD_MAC1;`
208			`end`
209			`PC_158: begin
210			`pc[15:8] <= dat8;`
211	38	robfinch	`if ((isRTI&m816)\|isRTL) begin`
212	32	robfinch	load_what <= `PC_2316;
213	38	robfinch	`inc_sp();`
214	32	robfinch	`state <= LOAD_MAC1;`
215			`end`
216			`else if (isRTS) // rts instruction`
217	38	robfinch	`next_state(RTS1);`
218	32	robfinch	`else // jmp (abs)`
219	38	robfinch	`next_state(BYTE_IFETCH);`
220	32	robfinch	`end`
221			`PC_2316: begin
222			`pc[23:16] <= dat8;`
223	38	robfinch	`if (isRTL) begin`
224			load_what <= `NOTHING;
225			`next_state(RTS1);`
226	32	robfinch	`end`
227	38	robfinch	`else begin`
228			load_what <= `NOTHING;
229			`next_state(BYTE_IFETCH);`
230			// load_what <= `PC_3124;
231			`// if (isRTI) begin`
232			`// inc_sp();`
233			`// end`
234			`// state <= LOAD_MAC1;`
235			`end`
236	32	robfinch	`end`
237			`PC_3124: begin
238			`pc[31:24] <= dat8;`
239			load_what <= `NOTHING;
240	38	robfinch	`next_state(BYTE_IFETCH);`
241	32	robfinch	`end`
242			`endif
243			`PC_310: begin
244			`pc <= dat;`
245			load_what <= `NOTHING;
246			`if (isRTI) begin`
247			km <= `FALSE;
248	35	robfinch	`ifdef DEBUG
249	32	robfinch	hist_capture <= `TRUE;
250	35	robfinch	`endif
251	32	robfinch	`end`
252	38	robfinch	`next_state(em ? BYTE_IFETCH : IFETCH);`
253			`// else // indirect jumps`
254			`// next_state(IFETCH);`
255	32	robfinch	`end`
256			`IA_310:
257			`begin`
258			`radr <= dat;`
259			`wadr <= dat;`
260			`wdat <= a;`
261			`if (isIY)`
262			`state <= IY3;`
263			else if (ir9==`ST_IX)
264			`state <= STORE1;`
265	36	robfinch	else if (ir9==`LEA_IX) begin
266			`res <= dat;`
267			`next_state(IFETCH);`
268			`end`
269	32	robfinch	`else begin`
270			load_what <= `WORD_310;
271			`state <= LOAD_MAC1;`
272			`end`
273			`end`
274			`ifdef SUPPORT_EM8
275			`IA_70:
276			`begin`
277			`radr <= radr34p1[33:2];`
278			`radr2LSB <= radr34p1[1:0];`
279			`ia[7:0] <= dat8;`
280			load_what <= `IA_158;
281			`state <= LOAD_MAC1;`
282			`end`
283			`IA_158:
284			`begin`
285			`ia[15:8] <= dat8;`
286	38	robfinch	`ia[31:16] <= {abs8[31:24],dbr};`
287			`if (isIY24\|isI24) begin`
288			`radr <= radr34p1[33:2];`
289			`radr2LSB <= radr34p1[1:0];`
290			load_what <= `IA_2316;
291			`state <= LOAD_MAC1;`
292			`end`
293			`else`
294			`state <= isIY ? BYTE_IY5 : BYTE_IX5;`
295	32	robfinch	`end`
296	38	robfinch	`IA_2316:
297			`begin`
298			`ia[23:16] <= dat8;`
299			`ia[31:24] <= abs8[31:24];`
300			`state <= isIY24 ? BYTE_IY5 : BYTE_IX5;`
301			`end`
302	32	robfinch	`endif
303			`endcase`
304			`end`
305			`endtask`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_tsk.v] - Blame information for rev 39