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// ============================================================================

//        __

//   \\__/ o\    (C) 2013  Robert Finch, Stratford

//    \  __ /    All rights reserved.

//     \/_//     robfinch<remove>@opencores.org

//       ||

//

// This source file is free software: you can redistribute it and/or modify 

// it under the terms of the GNU Lesser General Public License as published 

// by the Free Software Foundation, either version 3 of the License, or     

// (at your option) any later version.                                      

//                                                                          

// This source file is distributed in the hope that it will be useful,      

// but WITHOUT ANY WARRANTY; without even the implied warranty of           

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            

// GNU General Public License for more details.                             

//                                                                          

// You should have received a copy of the GNU General Public License        

// along with this program.  If not, see <http://www.gnu.org/licenses/>.    

//                                                                          

// ============================================================================

//

// Works for both eight bit and 32 bit modes

//

PLA1:

        if (unCachedData) begin

                cyc_o <= 1'b1;

                stb_o <= 1'b1;

                sel_o <= 4'hF;

                adr_o <= {radr,2'b00};

                state <= PLA2;

        end

        else if (dhit) begin

                res8 <= rdat8;

                res <= rdat;

                state <= IFETCH;

        end

        else

                dmiss <= `TRUE;

PLA2:

        if (ack_i) begin

                cyc_o <= 1'b0;

                stb_o <= 1'b0;

                sel_o <= 4'h0;

                adr_o <= 34'h0;

                res8 <= dati;

                res <= dat_i;

                state <= IFETCH;

        end

        else if (err_i) begin

                lock_o <= 1'b0;

                cyc_o <= 1'b0;

                stb_o <= 1'b0;

                we_o <= 1'b0;

                sel_o <= 4'h0;

                adr_o <= 34'h0;

                dat_o <= 32'h0;

                state <= BUS_ERROR;

        end