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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [pla.v] - Blame information for rev 5

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// Works for both eight bit and 32 bit modes
//
PLA1:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= PLA2;
        end
        else if (dhit) begin
                res8 <= rdat8;
                res <= rdat;
                state <= IFETCH;
        end
        else
                dmiss <= `TRUE;
PLA2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                res8 <= dati;
                res <= dat_i;
                state <= IFETCH;
        end

Line No.	Rev	Author	Line
1	5	robfinch	`// Works for both eight bit and 32 bit modes`
2			`//`
3			`PLA1:`
4			`if (unCachedData) begin`
5			`cyc_o <= 1'b1;`
6			`stb_o <= 1'b1;`
7			`sel_o <= 4'hF;`
8			`adr_o <= {radr,2'b00};`
9			`state <= PLA2;`
10			`end`
11			`else if (dhit) begin`
12			`res8 <= rdat8;`
13			`res <= rdat;`
14			`state <= IFETCH;`
15			`end`
16			`else`
17			dmiss <= `TRUE;
18			`PLA2:`
19			`if (ack_i) begin`
20			`cyc_o <= 1'b0;`
21			`stb_o <= 1'b0;`
22			`sel_o <= 4'h0;`
23			`adr_o <= 34'h0;`
24			`res8 <= dati;`
25			`res <= dat_i;`
26			`state <= IFETCH;`
27			`end`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [pla.v] - Blame information for rev 5