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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [plp.v] - Blame information for rev 21

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1 10 robfinch 
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2013  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
23 5 robfinch 
PLP1:
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        if (unCachedData) begin
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                sel_o <= 4'hF;
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                adr_o <= {radr,2'b00};
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                state <= PLP2;
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        end
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        else if (dhit) begin
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                cf <= rdat[0];
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                zf <= rdat[1];
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                im <= rdat[2];
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                df <= rdat[3];
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                bf <= rdat[4];
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                em <= rdat[29];
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                vf <= rdat[30];
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                nf <= rdat[31];
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                isp <= isp_inc;
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                radr <= isp_inc;
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                state <= IFETCH;
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        end
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        else
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                dmiss <= `TRUE;
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PLP2:
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        if (ack_i) begin
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                sel_o <= 4'h0;
51 13 robfinch 
                adr_o <= 34'd0;
52 5 robfinch 
                cf <= dat_i[0];
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                zf <= dat_i[1];
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                im <= dat_i[2];
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                df <= dat_i[3];
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                bf <= dat_i[4];
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                em <= dat_i[29];
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                vf <= dat_i[30];
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                nf <= dat_i[31];
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                isp <= isp_inc;
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                radr <= isp_inc;
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                state <= IFETCH;
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        end
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        else if (err_i) begin
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                lock_o <= 1'b0;
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                we_o <= 1'b0;
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                sel_o <= 4'h0;
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                adr_o <= 34'h0;
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                dat_o <= 32'h0;
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                state <= BUS_ERROR;
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        end

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