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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [plp.v] - Blame information for rev 5

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Line No. Rev Author Line
1 5 robfinch
PLP1:
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        if (unCachedData) begin
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                sel_o <= 4'hF;
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                adr_o <= {radr,2'b00};
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                state <= PLP2;
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        end
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        else if (dhit) begin
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                cf <= rdat[0];
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                zf <= rdat[1];
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                im <= rdat[2];
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                df <= rdat[3];
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                bf <= rdat[4];
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                em <= rdat[29];
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                vf <= rdat[30];
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                nf <= rdat[31];
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                isp <= isp_inc;
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                radr <= isp_inc;
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                state <= IFETCH;
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        end
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        else
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                dmiss <= `TRUE;
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PLP2:
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        if (ack_i) begin
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                sel_o <= 4'h0;
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                cf <= dat_i[0];
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                zf <= dat_i[1];
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                im <= dat_i[2];
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                df <= dat_i[3];
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                bf <= dat_i[4];
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                em <= dat_i[29];
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                vf <= dat_i[30];
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                nf <= dat_i[31];
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                isp <= isp_inc;
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                radr <= isp_inc;
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                state <= IFETCH;
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        end

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