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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002_defines.v] - Blame information for rev 35

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Line No. Rev Author Line
1 30 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
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//   \\__/ o\    (C) 2013  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
8
//
9
// rtf65002.v
10
//  - 32 bit CPU
11
//
12
// This source file is free software: you can redistribute it and/or modify 
13
// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
15
// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
23
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
26
//
27 35 robfinch
`ifndef RTF65002_DEFINES
28
`define RTF65002_DEFINES        1'b1
29
 
30 30 robfinch
`define TRUE            1'b1
31
`define FALSE           1'b0
32
 
33 35 robfinch
`define DEBUG           1'b1
34
 
35 32 robfinch
`define SUPPORT_ICACHE  1'b1
36
`define ICACHE_4K               1'b1
37
//`define ICACHE_16K            1'b1
38
//`define ICACHE_2WAY           1'b1
39
//`define SUPPORT_DCACHE        1'b1
40 30 robfinch
`define SUPPORT_BCD             1'b1
41
`define SUPPORT_DIVMOD          1'b1
42 32 robfinch
`define SUPPORT_EM8             1'b1
43
//`define SUPPORT_EXEC  1'b1
44 30 robfinch
`define SUPPORT_BERR    1'b1
45
`define SUPPORT_STRING  1'b1
46
`define SUPPORT_SHIFT   1'b1
47
 
48
`define RST_VECT        34'h3FFFFFFF8
49
`define NMI_VECT        34'h3FFFFFFF4
50
`define IRQ_VECT        34'h3FFFFFFF0
51
`define BRK_VECTNO      9'd0
52
`define SLP_VECTNO      9'd1
53
`define BYTE_RST_VECT   34'h00000FFFC
54
`define BYTE_NMI_VECT   34'h00000FFFA
55
`define BYTE_IRQ_VECT   34'h00000FFFE
56
 
57 32 robfinch
`define BRK                     9'h00
58
`define RTI                     9'h40
59
`define RTS                     9'h60
60
`define PHP                     9'h08
61
`define CLC                     9'h18
62
`define PLP                     9'h28
63
`define SEC                     9'h38
64
`define PHA                     9'h48
65
`define CLI                     9'h58
66
`define PLA                     9'h68
67
`define SEI                     9'h78
68
`define DEY                     9'h88
69
`define TYA                     9'h98
70
`define TAY                     9'hA8
71
`define CLV                     9'hB8
72
`define INY                     9'hC8
73
`define CLD                     9'hD8
74
`define INX                     9'hE8
75
`define SED                     9'hF8
76
`define ROR_ACC         9'h6A
77
`define TXA                     9'h8A
78
`define TXS                     9'h9A
79
`define TAX                     9'hAA
80
`define TSX                     9'hBA
81
`define DEX                     9'hCA
82
`define NOP                     9'hEA
83
`define TXY                     9'h9B
84
`define TYX                     9'hBB
85
`define TAS                     9'h1B
86
`define TSA                     9'h3B
87
`define TRS                     9'h8B
88
`define TSR                     9'hAB
89
`define STP                     9'hDB
90
`define NAT                     9'hFB
91
`define EMM                     9'hFB
92
`define INA                     9'h1A
93
`define DEA                     9'h3A
94 30 robfinch
 
95 32 robfinch
`define RR                      9'h02
96 30 robfinch
`define ADD_RR                  4'd0
97
`define SUB_RR                  4'd1
98
`define CMP_RR                  4'd2
99
`define AND_RR                  4'd3
100
`define EOR_RR                  4'd4
101
`define OR_RR                   4'd5
102
`define MUL_RR                  4'd8
103
`define MULS_RR                 4'd9
104
`define DIV_RR                  4'd10
105
`define DIVS_RR                 4'd11
106
`define MOD_RR                  4'd12
107
`define MODS_RR                 4'd13
108
`define ASL_RRR                 4'd14
109
`define LSR_RRR                 4'd15
110 32 robfinch
`define LD_RR           9'h7B
111 30 robfinch
 
112 32 robfinch
`define ADD_IMM8        9'h65           // 8 bit operand
113
`define ADD_IMM16       9'h79           // 16 bit operand
114
`define ADD_IMM32       9'h69           // 32 bit operand
115
`define ADD_ZPX         9'h75           // there is no ZP mode, use R0 to syntheisze
116
`define ADD_IX          9'h61
117
`define ADD_IY          9'h71
118
`define ADD_ABS         9'h6D
119
`define ADD_ABSX        9'h7D
120
`define ADD_RIND        9'h72
121
`define ADD_DSP         9'h63
122 30 robfinch
 
123 32 robfinch
`define SUB_IMM8        9'hE5
124
`define SUB_IMM16       9'hF9
125
`define SUB_IMM32       9'hE9
126
`define SUB_ZPX         9'hF5
127
`define SUB_IX          9'hE1
128
`define SUB_IY          9'hF1
129
`define SUB_ABS         9'hED
130
`define SUB_ABSX        9'hFD
131
`define SUB_RIND        9'hF2
132
`define SUB_DSP         9'hE3
133 30 robfinch
 
134
// CMP = SUB r0,....
135
 
136 32 robfinch
`define ADC_IMM         9'h69
137
`define ADC_ZP          9'h65
138
`define ADC_ZPX         9'h75
139
`define ADC_IX          9'h61
140
`define ADC_IY          9'h71
141
`define ADC_ABS         9'h6D
142
`define ADC_ABSX        9'h7D
143
`define ADC_ABSY        9'h79
144
`define ADC_I           9'h72
145 30 robfinch
 
146 32 robfinch
`define SBC_IMM         9'hE9
147
`define SBC_ZP          9'hE5
148
`define SBC_ZPX         9'hF5
149
`define SBC_IX          9'hE1
150
`define SBC_IY          9'hF1
151
`define SBC_ABS         9'hED
152
`define SBC_ABSX        9'hFD
153
`define SBC_ABSY        9'hF9
154
`define SBC_I           9'hF2
155 30 robfinch
 
156 32 robfinch
`define CMP_IMM8        9'hC5
157
`define CMP_IMM32       9'hC9
158
`define CMP_IMM         9'hC9
159
`define CMP_ZP          9'hC5
160
`define CMP_ZPX         9'hD5
161
`define CMP_IX          9'hC1
162
`define CMP_IY          9'hD1
163
`define CMP_ABS         9'hCD
164
`define CMP_ABSX        9'hDD
165
`define CMP_ABSY        9'hD9
166
`define CMP_I           9'hD2
167 30 robfinch
 
168
 
169 32 robfinch
`define LDA_IMM8        9'hA5
170
`define LDA_IMM16       9'hB9
171
`define LDA_IMM32       9'hA9
172 30 robfinch
 
173 32 robfinch
`define AND_IMM8        9'h25
174
`define AND_IMM16       9'h39
175
`define AND_IMM32       9'h29
176
`define AND_IMM         9'h29
177
`define AND_ZP          9'h25
178
`define AND_ZPX         9'h35
179
`define AND_IX          9'h21
180
`define AND_IY          9'h31
181
`define AND_ABS         9'h2D
182
`define AND_ABSX        9'h3D
183
`define AND_ABSY        9'h39
184
`define AND_RIND        9'h32
185
`define AND_I           9'h32
186
`define AND_DSP         9'h23
187 30 robfinch
 
188 32 robfinch
`define OR_IMM8         9'h05
189
`define OR_IMM16        9'h19
190
`define OR_IMM32        9'h09
191
`define OR_ZPX          9'h15
192
`define OR_IX           9'h01
193
`define OR_IY           9'h11
194
`define OR_ABS          9'h0D
195
`define OR_ABSX         9'h1D
196
`define OR_RIND         9'h12
197
`define OR_DSP          9'h03
198 30 robfinch
 
199 32 robfinch
`define ORA_IMM         9'h09
200
`define ORA_ZP          9'h05
201
`define ORA_ZPX         9'h15
202
`define ORA_IX          9'h01
203
`define ORA_IY          9'h11
204
`define ORA_ABS         9'h0D
205
`define ORA_ABSX        9'h1D
206
`define ORA_ABSY        9'h19
207
`define ORA_I           9'h12
208 30 robfinch
 
209 32 robfinch
`define EOR_IMM         9'h49
210
`define EOR_IMM8        9'h45
211
`define EOR_IMM16       9'h59
212
`define EOR_IMM32       9'h49
213
`define EOR_ZP          9'h45
214
`define EOR_ZPX         9'h55
215
`define EOR_IX          9'h41
216
`define EOR_IY          9'h51
217
`define EOR_ABS         9'h4D
218
`define EOR_ABSX        9'h5D
219
`define EOR_ABSY        9'h59
220
`define EOR_RIND        9'h52
221
`define EOR_I           9'h52
222
`define EOR_DSP         9'h43
223 30 robfinch
 
224
// LD is OR rt,r0,....
225
 
226 32 robfinch
`define ST_ZPX          9'h95
227
`define ST_IX           9'h81
228
`define ST_IY           9'h91
229
`define ST_ABS          9'h8D
230
`define ST_ABSX         9'h9D
231
`define ST_RIND         9'h92
232
`define ST_DSP          9'h83
233 30 robfinch
 
234 32 robfinch
`define ORB_ZPX         9'hB5
235
`define ORB_IX          9'hA1
236
`define ORB_IY          9'hB1
237
`define ORB_ABS         9'hAD
238
`define ORB_ABSX        9'hBD
239 30 robfinch
 
240 32 robfinch
`define STB_ZPX         9'h74
241
`define STB_ABS         9'h9C
242
`define STB_ABSX        9'h9E
243 30 robfinch
 
244
 
245 32 robfinch
//`define LDB_RIND      9'hB2   // Conflict with LDX #imm16
246 30 robfinch
 
247 32 robfinch
`define LDA_IMM         9'hA9
248
`define LDA_ZP          9'hA5
249
`define LDA_ZPX         9'hB5
250
`define LDA_IX          9'hA1
251
`define LDA_IY          9'hB1
252
`define LDA_ABS         9'hAD
253
`define LDA_ABSX        9'hBD
254
`define LDA_ABSY        9'hB9
255
`define LDA_I           9'hB2
256 30 robfinch
 
257 32 robfinch
`define STA_ZP          9'h85
258
`define STA_ZPX         9'h95
259
`define STA_IX          9'h81
260
`define STA_IY          9'h91
261
`define STA_ABS         9'h8D
262
`define STA_ABSX        9'h9D
263
`define STA_ABSY        9'h99
264
`define STA_I           9'h92
265 30 robfinch
 
266 32 robfinch
`define ASL_IMM8        9'h24
267
`define ASL_ACC         9'h0A
268
`define ASL_ZP          9'h06
269
`define ASL_RR          9'h06
270
`define ASL_ZPX         9'h16
271
`define ASL_ABS         9'h0E
272
`define ASL_ABSX        9'h1E
273 30 robfinch
 
274 32 robfinch
`define ROL_ACC         9'h2A
275
`define ROL_ZP          9'h26
276
`define ROL_RR          9'h26
277
`define ROL_ZPX         9'h36
278
`define ROL_ABS         9'h2E
279
`define ROL_ABSX        9'h3E
280 30 robfinch
 
281 32 robfinch
`define LSR_IMM8        9'h34
282
`define LSR_ACC         9'h4A
283
`define LSR_ZP          9'h46
284
`define LSR_RR          9'h46
285
`define LSR_ZPX         9'h56
286
`define LSR_ABS         9'h4E
287
`define LSR_ABSX        9'h5E
288 30 robfinch
 
289 32 robfinch
`define ROR_RR          9'h66
290
`define ROR_ZP          9'h66
291
`define ROR_ZPX         9'h76
292
`define ROR_ABS         9'h6E
293
`define ROR_ABSX        9'h7E
294 30 robfinch
 
295 32 robfinch
`define DEC_RR          9'hC6
296
`define DEC_ZP          9'hC6
297
`define DEC_ZPX         9'hD6
298
`define DEC_ABS         9'hCE
299
`define DEC_ABSX        9'hDE
300
`define INC_RR          9'hE6
301
`define INC_ZP          9'hE6
302
`define INC_ZPX         9'hF6
303
`define INC_ABS         9'hEE
304
`define INC_ABSX        9'hFE
305 30 robfinch
 
306 32 robfinch
`define BIT_IMM         9'h89
307
`define BIT_ZP          9'h24
308
`define BIT_ZPX         9'h34
309
`define BIT_ABS         9'h2C
310
`define BIT_ABSX        9'h3C
311 30 robfinch
 
312
// CMP = SUB r0,...
313
// BIT = AND r0,...
314 32 robfinch
`define BPL                     9'h10
315
`define BVC                     9'h50
316
`define BCC                     9'h90
317
`define BNE                     9'hD0
318
`define BMI                     9'h30
319
`define BVS                     9'h70
320
`define BCS                     9'hB0
321
`define BEQ                     9'hF0
322
`define BRL                     9'h82
323
`define BRA                     9'h80
324
`define BHI                     9'h13
325
`define BLS                     9'h33
326
`define BGE                     9'h93
327
`define BLT                     9'hB3
328
`define BGT                     9'hD3
329
`define BLE                     9'hF3
330 30 robfinch
 
331 32 robfinch
`define JML                     9'h5C
332
`define JMP                     9'h4C
333
`define JMP_IND         9'h6C
334
`define JMP_INDX        9'h7C
335
`define JMP_RIND        9'hD2
336
`define JSR                     9'h20
337
`define JSL                     9'h22
338
`define JSR_IND         9'h2C
339
`define JSR_INDX        9'hFC
340
`define JSR_RIND        9'hC2
341
`define RTS                     9'h60
342
`define RTL                     9'h6B
343
`define BSR                     9'h62
344
`define NOP                     9'hEA
345 30 robfinch
 
346 32 robfinch
`define BRK                     9'h00
347
`define PLX                     9'hFA
348
`define PLY                     9'h7A
349
`define PHX                     9'hDA
350
`define PHY                     9'h5A
351
`define WAI                     9'hCB
352
`define PUSH            9'h0B
353
`define POP                     9'h2B
354 30 robfinch
 
355 32 robfinch
`define LDX_IMM         9'hA2
356
`define LDX_ZP          9'hA6
357
`define LDX_ZPX         9'hB6
358
`define LDX_ZPY         9'hB6
359
`define LDX_ABS         9'hAE
360
`define LDX_ABSY        9'hBE
361 30 robfinch
 
362 32 robfinch
`define LDX_IMM32       9'hA2
363
`define LDX_IMM16       9'hB2
364
`define LDX_IMM8        9'hA6
365 30 robfinch
 
366 32 robfinch
`define LDY_IMM         9'hA0
367
`define LDY_ZP          9'hA4
368
`define LDY_ZPX         9'hB4
369
`define LDY_IMM32       9'hA0
370
`define LDY_ABS         9'hAC
371
`define LDY_ABSX        9'hBC
372 30 robfinch
 
373 32 robfinch
`define STX_ZP          9'h86
374
`define STX_ZPX         9'h96
375
`define STX_ZPY         9'h96
376
`define STX_ABS         9'h8E
377 30 robfinch
 
378 32 robfinch
`define STY_ZP          9'h84
379
`define STY_ZPX         9'h94
380
`define STY_ABS         9'h8C
381 30 robfinch
 
382 32 robfinch
`define STZ_ZP          9'h64
383
`define STZ_ZPX         9'h74
384
`define STZ_ABS         9'h9C
385
`define STZ_ABSX        9'h9E
386 30 robfinch
 
387 32 robfinch
`define CPX_IMM         9'hE0
388
`define CPX_IMM32       9'hE0
389
`define CPX_ZP          9'hE4
390
`define CPX_ZPX         9'hE4
391
`define CPX_ABS         9'hEC
392
`define CPY_IMM         9'hC0
393
`define CPY_IMM32       9'hC0
394
`define CPY_ZP          9'hC4
395
`define CPY_ZPX         9'hC4
396
`define CPY_ABS         9'hCC
397 30 robfinch
 
398 32 robfinch
`define TRB_ZP          9'h14
399
`define TRB_ZPX         9'h14
400
`define TRB_ABS         9'h1C
401
`define TSB_ZP          9'h04
402
`define TSB_ZPX         9'h04
403
`define TSB_ABS         9'h0C
404 30 robfinch
 
405 32 robfinch
`define BAZ                     9'hC1
406
`define BXZ                     9'hD1
407
`define BEQ_RR          9'hE2
408
`define INT0            9'hDC
409
`define INT1            9'hDD
410
`define SUB_SP8         9'h85
411
`define SUB_SP16        9'h99
412
`define SUB_SP32        9'h89
413
`define MVP                     9'h44
414
`define MVN                     9'h54
415
`define STS                     9'h64
416
`define EXEC            9'hEB
417
`define ATNI            9'h4B
418 35 robfinch
`define MDR                     9'h3C
419 30 robfinch
 
420 35 robfinch
// Page Two Opcodes
421 32 robfinch
`define PG2                     9'h42
422 30 robfinch
 
423 32 robfinch
`define TOFF            9'h118
424
`define TON                     9'h138
425
`define MUL_IMM8        9'h105
426
`define MUL_IMM16       9'h119
427
`define MUL_IMM32       9'h109
428
`define DIV_IMM8        9'h145
429
`define DIV_IMM16       9'h159
430
`define DIV_IMM32       9'h149
431
`define MOD_IMM8        9'h185
432
`define MOD_IMM16       9'h199
433
`define MOD_IMM32       9'h189
434
`define PUSHA           9'h10B
435
`define POPA            9'h12B
436
`define BMS_ZPX         9'h106
437
`define BMS_ABS         9'h10E
438
`define BMS_ABSX        9'h11E
439
`define BMC_ZPX         9'h126
440
`define BMC_ABS         9'h12E
441
`define BMC_ABSX        9'h13E
442
`define BMF_ZPX         9'h146
443
`define BMF_ABS         9'h14E
444
`define BMF_ABSX        9'h15E
445
`define BMT_ZPX         9'h166
446
`define BMT_ABS         9'h16E
447
`define BMT_ABSX        9'h17E
448
`define HOFF            9'h158
449
`define CMPS            9'h144
450 30 robfinch
 
451 32 robfinch
`define NOTHING         5'd0
452
`define SR_70           5'd1
453
`define SR_310          5'd2
454
`define BYTE_70         5'd3
455
`define WORD_310        5'd4
456
`define PC_70           5'd5
457
`define PC_158          5'd6
458
`define PC_2316         5'd7
459
`define PC_3124         5'd8
460
`define PC_310          5'd9
461
`define WORD_311        5'd10
462
`define IA_310          5'd11
463
`define IA_70           5'd12
464
`define IA_158          5'd13
465
`define BYTE_71         5'd14
466
`define WORD_312        5'd15
467
`define WORD_313        5'd16
468
`define WORD_314        5'd17
469
 
470 30 robfinch
`define STW_DEF         6'h0
471
`define STW_ACC         6'd1
472
`define STW_X           6'd2
473
`define STW_Y           6'd3
474
`define STW_PC          6'd4
475
`define STW_PC2         6'd5
476
`define STW_PCHWI       6'd6
477
`define STW_SR          6'd7
478
`define STW_RFA         6'd8
479
`define STW_RFA8        6'd9
480 35 robfinch
`define STW_A           6'd10
481
`define STW_B           6'd11
482
`define STW_CALC        6'd12
483
`define STW_OPC         6'd13
484
 
485 30 robfinch
`define STW_ACC8        6'd16
486
`define STW_X8          6'd17
487
`define STW_Y8          6'd18
488
`define STW_PC3124      6'd19
489
`define STW_PC2316      6'd20
490
`define STW_PC158       6'd21
491
`define STW_PC70        6'd22
492
`define STW_SR70        6'd23
493 32 robfinch
`define STW_Z8          6'd24
494 35 robfinch
`define STW_DEF8        6'd25
495
 
496
`endif

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