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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002_dtagmem.v] - Blame information for rev 35

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Line No. Rev Author Line
1 30 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2013  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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module rtf65002_dtagmem(wclk, wr, wadr, cr, rclk, radr, hit);
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input wclk;
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input wr;
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input [31:0] wadr;
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input cr;
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input rclk;
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input [31:0] radr;
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output hit;
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reg [31:0] rradr;
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wire [31:0] tag;
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syncRam512x32_1rw1r u1
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        (
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                .wrst(1'b0),
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                .wclk(wclk),
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                .wce(1'b1),
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                .we(wr),
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                .wadr(wadr[10:2]),
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                .i({wadr[31:1],cr}),
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                .wo(),
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                .rrst(1'b0),
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                .rclk(rclk),
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                .rce(1'b1),
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                .radr(radr[10:2]),
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                .o(tag)
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        );
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always @(posedge rclk)
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        rradr <= radr;
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assign hit = tag[31:11]==rradr[31:11] && tag[0];
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endmodule

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