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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002_string.v] - Blame information for rev 32
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robfinch |
// ============================================================================
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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`ifdef SUPPORT_STRING
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MVN3:
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begin
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state <= IFETCH;
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res <= alu_out;
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if (acc==32'hFFFFFFFF)
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pc <= pc + 32'd1;
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end
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CMPS1:
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begin
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state <= IFETCH;
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res <= alu_out;
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if (a!=b || acc==32'hFFFFFFFF) begin
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cf <= !(ltu|eq);
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nf <= lt;
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vf <= 1'b0;
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zf <= eq;
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pc <= pc + 32'd1;
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end
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end
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`endif
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