OpenCores
URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002_string.v] - Blame information for rev 38

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 32 robfinch
// ============================================================================
2
//        __
3 38 robfinch
//   \\__/ o\    (C) 2013,2014  Robert Finch, Stratford
4 32 robfinch
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch<remove>@opencores.org
6
//       ||
7
//
8
// This source file is free software: you can redistribute it and/or modify 
9
// it under the terms of the GNU Lesser General Public License as published 
10
// by the Free Software Foundation, either version 3 of the License, or     
11
// (at your option) any later version.                                      
12
//                                                                          
13
// This source file is distributed in the hope that it will be useful,      
14
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
15
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
16
// GNU General Public License for more details.                             
17
//                                                                          
18
// You should have received a copy of the GNU General Public License        
19
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
20
//                                                                          
21
// ============================================================================
22
//
23
`ifdef SUPPORT_STRING
24
MVN3:
25
        begin
26 38 robfinch
                next_state(IFETCH);
27 32 robfinch
                res <= alu_out;
28 38 robfinch
                if (&acc)
29
                        pc <= pc + pc_inc;
30 32 robfinch
        end
31
CMPS1:
32
        begin
33 38 robfinch
                next_state(IFETCH);
34 32 robfinch
                res <= alu_out;
35 38 robfinch
                if (a!=b || &acc) begin
36 32 robfinch
                        cf <= !(ltu|eq);
37
                        nf <= lt;
38
                        vf <= 1'b0;
39
                        zf <= eq;
40 38 robfinch
                        pc <= pc + pc_inc;
41 32 robfinch
                end
42
        end
43
`endif
44 38 robfinch
`ifdef SUPPORT_816
45
MVN816:
46
        begin
47
                next_state(BYTE_IFETCH);
48
                if (&acc[15:0]) begin
49
                        pc <= pc + pc_inc8;
50
                        dbr <= ir[15:8];
51
                end
52
        end
53
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.