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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002_tb.v] - Blame information for rev 36

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module rtf65002_tb();
 
integer n;
reg rst;
reg clk;
reg nmi;
wire wr;
wire [5:0] bl;
wire [3:0] sel;
wire [33:0] a;
tri [31:0] d;
wire [31:0] dato;
wire [31:0] dati;
wire [2:0] cti;
wire cyc;
wire stb;
wire ack;
wire [7:0] udo;
wire btrm_ack;
wire [31:0] btrm_dato;
wire bas_ack;
wire [31:0] bas_dato;
wire tc_ack;
wire [31:0] tc_dato;
wire sema_ack;
wire [31:0] sema_dat;
wire ga_ack;
wire [31:0] ga_dat;
 
initial begin
        clk = 1;
        rst = 0;
        nmi = 0;
        #100 rst = 1;
        #100 rst = 0;
        #500 nmi = 0;
        #10 nmi = 0;
end
 
always #1 clk = ~clk;   // 500 MHz
 
rtf65002d cpu0 (
        .rst_i(rst),
        .clk_i(clk),
        .nmi_i(nmi),
        .irq_i(1'b0),
        .bte_o(),
        .cti_o(cti),
        .bl_o(bl),
        .lock_o(),
        .cyc_o(cyc),
        .stb_o(stb),
        .ack_i(ack),
        .we_o(wr),
        .sel_o(sel),
        .adr_o(a),
        .dat_i(dati),
        .dat_o(dato)
);
 
wire uartcs = cyc && stb && a[33:8]==26'h00000BF;
wire romcs = ~(cyc && stb && a[33:20]==14'h0FFF);
wire ramcs = ~(cyc && stb && (a[33:14]==20'h00 || (a[33:28]!=6'h3F && a[33:28]!=6'h0 && a[33:28]!=6'h0F)));
wire romcs1 = 1'b1;//~(cyc && stb && a[33:13]==21'h07); // E000
wire bas_cs = (cyc && stb && a[33:14]==20'h03);
wire tc_cs = (cyc && stb && (a[33:18]==16'hFFD0 || a[33:18]==16'hFFDA ||a[33:18]==16'hFFD1 || a[33:18]==16'hFFD2));
wire leds_cs = (cyc && stb && a[33:2]==32'hFFDC0600);
wire configrec_cs = (cyc && stb && a[33:6]==28'hFFDCFFF);
 
assign d = wr ? dato : 32'bz;
assign dati = ~romcs ? btrm_dato : 32'bz;
assign dati = ~ramcs ? d : 32'bz;
assign dati = uartcs ? {4{udo}} : 32'bz;
assign dati = ~romcs1 ? d : 32'bz;
assign dati = bas_cs ? bas_dato : 32'bz;
assign dati = tc_cs ? tc_dato : 32'bz;
assign dati = configrec_cs ? 32'h00000FDF : 32'bz;
assign dati = sema_ack ? sema_dat : 32'bz;
assign dati = ga_ack ? ga_dat : 32'bz;
 
assign ack =
        configrec_cs |
        leds_cs |
        tc_ack |
        sema_ack |
        ga_ack |
        bas_ack |
        btrm_ack |
        ~ramcs |
        ~romcs1 |
        uartcs
        ;
 
//rom2Kx32 #(.MEMFILE("t65c.mem")) rom0(.ce(romcs), .oe(wr), .addr(a[12:2]), .d(d));
rom2Kx32 #(.MEMFILE("t65c.mem")) rom1(.ce(romcs1), .oe(wr), .addr(a[12:2]), .d(d));
ram8Kx32 ram0 (.clk(clk), .ce(ramcs), .oe(wr), .we(~wr), .sel(sel), .addr(a[14:2]), .d(d));
uart uart0(.clk(clk), .cs(uartcs), .wr(wr), .a(a[2:0]), .di(dato[7:0]), .do(udo));
bootrom ubr1 (.rst_i(rst), .clk_i(clk), .cti_i(cti), .cyc_i(cyc), .stb_i(stb), .ack_o(btrm_ack), .adr_i(a), .dat_o(btrm_dato), .perr());
basic_rom ubas1(.rst_i(rst), .clk_i(clk), .cti_i(cti), .cyc_i(cyc), .stb_i(stb), .ack_o(bas_ack), .adr_i(a), .dat_o(bas_dato), .perr());
rtfTextController tc1 (
        .rst_i(rst),
        .clk_i(clk),
        .cyc_i(cyc),
        .stb_i(stb),
        .ack_o(tc_ack),
        .we_i(wr),
        .adr_i(a),
        .dat_i(dato),
        .dat_o(tc_dato),
        .lp(),
        .curpos(),
        .vclk(1'b0),
        .hsync(1'b0),
        .vsync(1'b0),
        .blank(1'b0),
        .border(1'b0),
        .rgbIn(),
        .rgbOut()
);
 
sema_mem usm1
(
        .rst_i(rst),
        .clk_i(clk),
        .cyc_i(cyc),
        .stb_i(stb),
        .ack_o(sema_ack),
        .we_i(wr),
        .adr_i(a),
        .dat_i(dato),
        .dat_o(sema_dat)
);
 
rtfGraphicsAccelerator uga1 (
.rst_i(rst),
.clk_i(clk),
 
.s_cyc_i(cyc),
.s_stb_i(stb),
.s_we_i(wr),
.s_ack_o(ga_ack),
.s_sel_i(sel),
.s_adr_i(a),
.s_dat_i(dato),
.s_dat_o(ga_dat),
 
.m_cyc_o(),
.m_stb_o(),
.m_we_o(),
.m_ack_i(1'b1),
.m_sel_o(),
.m_adr_o(),
.m_dat_i(),
.m_dat_o()
);
 
always @(posedge clk) begin
        if (rst)
                n = 0;
        else
                n = n + 1;
        if ((n & 7)==0)
                $display("t   n  cti cyc we   addr din adnx do re vma wr ird sync vma nmi irq  PC  IR A  X  Y  SP nvmdizcb\n");
        $display("%d %d %b  %b%b  %c  %h %h %h %h %h pc=%h ir=%h acc=%h x=%h y=%h sp=%h sp8=%h %b%b%b%b%b%b%b%b %s %b %b %b %b %b %b",
                $time, n, cpu0.cti_o, cpu0.cyc_o, cpu0.ack_i, cpu0.we_o?"W":" ", cpu0.adr_o, cpu0.dat_i, cpu0.dat_o, cpu0.res, cpu0.res8, cpu0.pc, cpu0.ir,
                cpu0.acc, cpu0.x, cpu0.y, cpu0.isp, cpu0.sp,
                cpu0.nf, cpu0.vf, cpu0.df, cpu0.im, cpu0.zf, cpu0.cf, cpu0.bf, cpu0.em, cpu0.fnStateName(cpu0.state), cpu0.imiss, cpu0.ihit,cpu0.hit0,cpu0.hit1,cpu0.imiss,ubr1.cs);
end
 
endmodule
 
/* ---------------------------------------------------------------
        rom2kx32.v -- external async 8Kx8 ROM Verilog model
        (simulation only)
 
        Note this module is a functional model, with no timing, and
  is only suitable for simulation, not synthesis.
--------------------------------------------------------------- */
 
module rom2Kx32(ce, oe, addr, d);
parameter MEMFILE = "t65002d.mem";
        input                   ce;     // active low chip enable
        input                   oe;     // active low output enable
        input   [10:0]   addr;   // byte address
        output  [31:0]   d;              // tri-state data I/O
        tri [31:0] d;
 
        reg             [7:0]    mem [0:8191];
 
        initial begin
                $readmemh (MEMFILE, mem);
//              $readmemh ("t65c.mem", mem);
                $display ("Loaded t65002d.mem");
                $display (" 000000: %h %h %h %h %h %h %h %h",
                        mem[0], mem[1], mem[2], mem[3], mem[4], mem[5], mem[6], mem[7]);
        end
 
        assign d = (~oe & ~ce) ? {mem[{addr,2'b11}],mem[{addr,2'b10}],mem[{addr,2'b01}],mem[{addr,2'b00}]} : 32'bz;
/*
        always @(oe or ce or addr) begin
//              $display (" 000000: %h %h %h %h %h %h %h %h %h %h",
//                      mem[0], mem[1], mem[2], mem[3], mem[4], mem[5], mem[6], mem[7], mem[8], mem[9]);
                $display (" read %h: %h", addr, mem[addr]);
        end
*/
endmodule
 
/* ---------------------------------------------------------------
        ram32kx8.v -- external sync 32Kx8 RAM Verilog model
        (simulation only)
 
        Note this module is a functional model, with no timing, and
  is only suitable for simulation, not synthesis.
--------------------------------------------------------------- */
 
module ram8Kx32(clk, ce, oe, we, sel, addr, d);
        input clk;
        input                   ce;             // active low chip enable
        input                   oe;             // active low output enable
        input                   we;             // active low write enable
        input [3:0] sel;         // byte lane selects
        input   [12:0]   addr;   // byte address
        output  [31:0]   d;              // tri-state data I/O
        tri [31:0] d;
 
        reg             [31:0]   mem [0:65535];
        integer nn;
 
        initial begin
                for (nn = 0; nn < 8192; nn = nn + 1)
                        mem[nn] <= 32'b0;
        end
 
        assign d = (~oe & ~ce & we) ? mem[addr] : 32'bz;
 
        always @(posedge clk) begin
                if (clk) begin
                        if (~ce & ~we) begin
                                if (sel[0]) mem[addr][7:0] <= d[7:0];
                                if (sel[1]) mem[addr][15:8] <= d[15:8];
                                if (sel[2]) mem[addr][23:16] <= d[23:16];
                                if (sel[3]) mem[addr][31:24] <= d[31:24];
                                $display (" wrote: %h with %h", addr, d);
                        end
                        if (~ce & we & ~oe)
                                $display (" read: %h val %h", addr, d);
                end
        end
/*
        always @(we or oe or ce or addr) begin
                if (ce==0)
                        $display (" 000000: %h %h %h %h %h %h %h %h %h %h",
                                mem[0], mem[1], mem[2], mem[3], mem[4], mem[5], mem[6], mem[7], mem[8], mem[9]);
        end
*/
endmodule
 
module uart(clk, cs, wr, a, di, do);
        input clk;
        input cs;
        input wr;
        input [2:0] a;
        input [7:0] di;
        output reg [7:0] do;
//      reg [7:0] do;
 
        reg [127:0] msg;
        integer msgn;
        integer logf,r;
 
        initial begin
                msgn <= 0;
        end
 
        always @(posedge clk)
                if (cs & wr) begin
                        if (di==8'h0A) begin
                                $display(" ");
                                $display("%s", msg);
                                $display (" ");
                                $stop;
                                msgn <= 0;
                                msg <= 0;
                        end
                        else begin
                                case(msgn)
                                0: msg[127:120] <= di;
                                1: msg[119:112] <= di;
                                2:      msg[111:104] <= di;
                                3:      msg[103:96] <= di;
                                4:      msg[95:88] <= di;
                                5:      msg[87:80] <= di;
                                6:      msg[79:72] <= di;
                                7:      msg[71:64] <= di;
                                endcase
                                msgn <= msgn + 1;
                        end
                end
 
//      always @(posedge clk)
//              if (cs & wr) begin
//                      logf = $fopen("uart_in", "a");
//                      r = $fdisplay(logf, "%h", di);
//                      $fclose(logf);
//              end
 
        always @(a)
        begin
                case(a)
                default:
                        do <= 8'h00;
                endcase
        end
 
//      assign do = 8'h00;
 
endmodule

Line No.	Rev	Author	Line
1	5	robfinch	`module rtf65002_tb();`
2
3			`integer n;`
4			`reg rst;`
5			`reg clk;`
6			`reg nmi;`
7			`wire wr;`
8			`wire [5:0] bl;`
9			`wire [3:0] sel;`
10			`wire [33:0] a;`
11			`tri [31:0] d;`
12			`wire [31:0] dato;`
13			`wire [31:0] dati;`
14	20	robfinch	`wire [2:0] cti;`
15	5	robfinch	`wire cyc;`
16			`wire stb;`
17			`wire ack;`
18			`wire [7:0] udo;`
19	20	robfinch	`wire btrm_ack;`
20			`wire [31:0] btrm_dato;`
21	36	robfinch	`wire bas_ack;`
22			`wire [31:0] bas_dato;`
23			`wire tc_ack;`
24			`wire [31:0] tc_dato;`
25			`wire sema_ack;`
26			`wire [31:0] sema_dat;`
27			`wire ga_ack;`
28			`wire [31:0] ga_dat;`
29	5	robfinch
30			`initial begin`
31			`clk = 1;`
32			`rst = 0;`
33			`nmi = 0;`
34			`#100 rst = 1;`
35			`#100 rst = 0;`
36	36	robfinch	`#500 nmi = 0;`
37	5	robfinch	`#10 nmi = 0;`
38			`end`
39
40			`always #1 clk = ~clk; // 500 MHz`
41
42			`rtf65002d cpu0 (`
43			`.rst_i(rst),`
44			`.clk_i(clk),`
45			`.nmi_i(nmi),`
46			`.irq_i(1'b0),`
47			`.bte_o(),`
48	20	robfinch	`.cti_o(cti),`
49	5	robfinch	`.bl_o(bl),`
50			`.lock_o(),`
51			`.cyc_o(cyc),`
52			`.stb_o(stb),`
53	20	robfinch	`.ack_i(ack),`
54	5	robfinch	`.we_o(wr),`
55			`.sel_o(sel),`
56			`.adr_o(a),`
57			`.dat_i(dati),`
58			`.dat_o(dato)`
59			`);`
60
61	36	robfinch	`wire uartcs = cyc && stb && a[33:8]==26'h00000BF;`
62			`wire romcs = ~(cyc && stb && a[33:20]==14'h0FFF);`
63			`wire ramcs = ~(cyc && stb && (a[33:14]==20'h00 \|\| (a[33:28]!=6'h3F && a[33:28]!=6'h0 && a[33:28]!=6'h0F)));`
64			`wire romcs1 = 1'b1;//~(cyc && stb && a[33:13]==21'h07); // E000`
65			`wire bas_cs = (cyc && stb && a[33:14]==20'h03);`
66			`wire tc_cs = (cyc && stb && (a[33:18]==16'hFFD0 \|\| a[33:18]==16'hFFDA \|\|a[33:18]==16'hFFD1 \|\| a[33:18]==16'hFFD2));`
67			`wire leds_cs = (cyc && stb && a[33:2]==32'hFFDC0600);`
68			`wire configrec_cs = (cyc && stb && a[33:6]==28'hFFDCFFF);`
69	5	robfinch
70			`assign d = wr ? dato : 32'bz;`
71	20	robfinch	`assign dati = ~romcs ? btrm_dato : 32'bz;`
72	5	robfinch	`assign dati = ~ramcs ? d : 32'bz;`
73			`assign dati = uartcs ? {4{udo}} : 32'bz;`
74			`assign dati = ~romcs1 ? d : 32'bz;`
75	36	robfinch	`assign dati = bas_cs ? bas_dato : 32'bz;`
76			`assign dati = tc_cs ? tc_dato : 32'bz;`
77			`assign dati = configrec_cs ? 32'h00000FDF : 32'bz;`
78			`assign dati = sema_ack ? sema_dat : 32'bz;`
79			`assign dati = ga_ack ? ga_dat : 32'bz;`
80	5	robfinch
81	20	robfinch	`assign ack =`
82	36	robfinch	`configrec_cs \|`
83			`leds_cs \|`
84			`tc_ack \|`
85			`sema_ack \|`
86			`ga_ack \|`
87			`bas_ack \|`
88	20	robfinch	`btrm_ack \|`
89			`~ramcs \|`
90			`~romcs1 \|`
91			`uartcs`
92			`;`
93
94			`//rom2Kx32 #(.MEMFILE("t65c.mem")) rom0(.ce(romcs), .oe(wr), .addr(a[12:2]), .d(d));`
95	5	robfinch	`rom2Kx32 #(.MEMFILE("t65c.mem")) rom1(.ce(romcs1), .oe(wr), .addr(a[12:2]), .d(d));`
96			`ram8Kx32 ram0 (.clk(clk), .ce(ramcs), .oe(wr), .we(~wr), .sel(sel), .addr(a[14:2]), .d(d));`
97			`uart uart0(.clk(clk), .cs(uartcs), .wr(wr), .a(a[2:0]), .di(dato[7:0]), .do(udo));`
98	20	robfinch	`bootrom ubr1 (.rst_i(rst), .clk_i(clk), .cti_i(cti), .cyc_i(cyc), .stb_i(stb), .ack_o(btrm_ack), .adr_i(a), .dat_o(btrm_dato), .perr());`
99	36	robfinch	`basic_rom ubas1(.rst_i(rst), .clk_i(clk), .cti_i(cti), .cyc_i(cyc), .stb_i(stb), .ack_o(bas_ack), .adr_i(a), .dat_o(bas_dato), .perr());`
100			`rtfTextController tc1 (`
101			`.rst_i(rst),`
102			`.clk_i(clk),`
103			`.cyc_i(cyc),`
104			`.stb_i(stb),`
105			`.ack_o(tc_ack),`
106			`.we_i(wr),`
107			`.adr_i(a),`
108			`.dat_i(dato),`
109			`.dat_o(tc_dato),`
110			`.lp(),`
111			`.curpos(),`
112			`.vclk(1'b0),`
113			`.hsync(1'b0),`
114			`.vsync(1'b0),`
115			`.blank(1'b0),`
116			`.border(1'b0),`
117			`.rgbIn(),`
118			`.rgbOut()`
119			`);`
120	5	robfinch
121	36	robfinch	`sema_mem usm1`
122			`(`
123			`.rst_i(rst),`
124			`.clk_i(clk),`
125			`.cyc_i(cyc),`
126			`.stb_i(stb),`
127			`.ack_o(sema_ack),`
128			`.we_i(wr),`
129			`.adr_i(a),`
130			`.dat_i(dato),`
131			`.dat_o(sema_dat)`
132			`);`
133
134			`rtfGraphicsAccelerator uga1 (`
135			`.rst_i(rst),`
136			`.clk_i(clk),`
137
138			`.s_cyc_i(cyc),`
139			`.s_stb_i(stb),`
140			`.s_we_i(wr),`
141			`.s_ack_o(ga_ack),`
142			`.s_sel_i(sel),`
143			`.s_adr_i(a),`
144			`.s_dat_i(dato),`
145			`.s_dat_o(ga_dat),`
146
147			`.m_cyc_o(),`
148			`.m_stb_o(),`
149			`.m_we_o(),`
150			`.m_ack_i(1'b1),`
151			`.m_sel_o(),`
152			`.m_adr_o(),`
153			`.m_dat_i(),`
154			`.m_dat_o()`
155			`);`
156
157	5	robfinch	`always @(posedge clk) begin`
158			`if (rst)`
159			`n = 0;`
160			`else`
161			`n = n + 1;`
162			`if ((n & 7)==0)`
163			`$display("t n cti cyc we addr din adnx do re vma wr ird sync vma nmi irq PC IR A X Y SP nvmdizcb\n");`
164	36	robfinch	`$display("%d %d %b %b%b %c %h %h %h %h %h pc=%h ir=%h acc=%h x=%h y=%h sp=%h sp8=%h %b%b%b%b%b%b%b%b %s %b %b %b %b %b %b",`
165			`$time, n, cpu0.cti_o, cpu0.cyc_o, cpu0.ack_i, cpu0.we_o?"W":" ", cpu0.adr_o, cpu0.dat_i, cpu0.dat_o, cpu0.res, cpu0.res8, cpu0.pc, cpu0.ir,`
166	5	robfinch	`cpu0.acc, cpu0.x, cpu0.y, cpu0.isp, cpu0.sp,`
167	36	robfinch	`cpu0.nf, cpu0.vf, cpu0.df, cpu0.im, cpu0.zf, cpu0.cf, cpu0.bf, cpu0.em, cpu0.fnStateName(cpu0.state), cpu0.imiss, cpu0.ihit,cpu0.hit0,cpu0.hit1,cpu0.imiss,ubr1.cs);`
168	5	robfinch	`end`
169
170			`endmodule`
171
172			`/* ---------------------------------------------------------------`
173			`rom2kx32.v -- external async 8Kx8 ROM Verilog model`
174			`(simulation only)`
175
176			`Note this module is a functional model, with no timing, and`
177			`is only suitable for simulation, not synthesis.`
178			`--------------------------------------------------------------- */`
179
180			`module rom2Kx32(ce, oe, addr, d);`
181			`parameter MEMFILE = "t65002d.mem";`
182			`input ce; // active low chip enable`
183			`input oe; // active low output enable`
184			`input [10:0] addr; // byte address`
185			`output [31:0] d; // tri-state data I/O`
186			`tri [31:0] d;`
187
188			`reg [7:0] mem [0:8191];`
189
190			`initial begin`
191			`$readmemh (MEMFILE, mem);`
192			`// $readmemh ("t65c.mem", mem);`
193			`$display ("Loaded t65002d.mem");`
194			`$display (" 000000: %h %h %h %h %h %h %h %h",`
195			`mem[0], mem[1], mem[2], mem[3], mem[4], mem[5], mem[6], mem[7]);`
196			`end`
197
198			`assign d = (~oe & ~ce) ? {mem[{addr,2'b11}],mem[{addr,2'b10}],mem[{addr,2'b01}],mem[{addr,2'b00}]} : 32'bz;`
199			`/*`
200			`always @(oe or ce or addr) begin`
201			`// $display (" 000000: %h %h %h %h %h %h %h %h %h %h",`
202			`// mem[0], mem[1], mem[2], mem[3], mem[4], mem[5], mem[6], mem[7], mem[8], mem[9]);`
203			`$display (" read %h: %h", addr, mem[addr]);`
204			`end`
205			`*/`
206			`endmodule`
207
208			`/* ---------------------------------------------------------------`
209			`ram32kx8.v -- external sync 32Kx8 RAM Verilog model`
210			`(simulation only)`
211
212			`Note this module is a functional model, with no timing, and`
213			`is only suitable for simulation, not synthesis.`
214			`--------------------------------------------------------------- */`
215
216			`module ram8Kx32(clk, ce, oe, we, sel, addr, d);`
217			`input clk;`
218			`input ce; // active low chip enable`
219			`input oe; // active low output enable`
220			`input we; // active low write enable`
221			`input [3:0] sel; // byte lane selects`
222			`input [12:0] addr; // byte address`
223			`output [31:0] d; // tri-state data I/O`
224			`tri [31:0] d;`
225
226	36	robfinch	`reg [31:0] mem [0:65535];`
227	5	robfinch	`integer nn;`
228
229			`initial begin`
230			`for (nn = 0; nn < 8192; nn = nn + 1)`
231			`mem[nn] <= 32'b0;`
232			`end`
233
234			`assign d = (~oe & ~ce & we) ? mem[addr] : 32'bz;`
235
236			`always @(posedge clk) begin`
237			`if (clk) begin`
238			`if (~ce & ~we) begin`
239			`if (sel[0]) mem[addr][7:0] <= d[7:0];`
240			`if (sel[1]) mem[addr][15:8] <= d[15:8];`
241			`if (sel[2]) mem[addr][23:16] <= d[23:16];`
242			`if (sel[3]) mem[addr][31:24] <= d[31:24];`
243			`$display (" wrote: %h with %h", addr, d);`
244			`end`
245			`if (~ce & we & ~oe)`
246			`$display (" read: %h val %h", addr, d);`
247			`end`
248			`end`
249			`/*`
250			`always @(we or oe or ce or addr) begin`
251			`if (ce==0)`
252			`$display (" 000000: %h %h %h %h %h %h %h %h %h %h",`
253			`mem[0], mem[1], mem[2], mem[3], mem[4], mem[5], mem[6], mem[7], mem[8], mem[9]);`
254			`end`
255			`*/`
256			`endmodule`
257
258			`module uart(clk, cs, wr, a, di, do);`
259			`input clk;`
260			`input cs;`
261			`input wr;`
262			`input [2:0] a;`
263			`input [7:0] di;`
264			`output reg [7:0] do;`
265			`// reg [7:0] do;`
266
267			`reg [127:0] msg;`
268			`integer msgn;`
269			`integer logf,r;`
270
271			`initial begin`
272			`msgn <= 0;`
273			`end`
274
275			`always @(posedge clk)`
276			`if (cs & wr) begin`
277			`if (di==8'h0A) begin`
278			`$display(" ");`
279			`$display("%s", msg);`
280			`$display (" ");`
281			`$stop;`
282			`msgn <= 0;`
283			`msg <= 0;`
284			`end`
285			`else begin`
286			`case(msgn)`
287			`0: msg[127:120] <= di;`
288			`1: msg[119:112] <= di;`
289			`2: msg[111:104] <= di;`
290			`3: msg[103:96] <= di;`
291			`4: msg[95:88] <= di;`
292			`5: msg[87:80] <= di;`
293			`6: msg[79:72] <= di;`
294			`7: msg[71:64] <= di;`
295			`endcase`
296			`msgn <= msgn + 1;`
297			`end`
298			`end`
299
300			`// always @(posedge clk)`
301			`// if (cs & wr) begin`
302			`// logf = $fopen("uart_in", "a");`
303			`// r = $fdisplay(logf, "%h", di);`
304			`// $fclose(logf);`
305			`// end`
306
307			`always @(a)`
308			`begin`
309			`case(a)`
310			`default:`
311			`do <= 8'h00;`
312			`endcase`
313			`end`
314
315			`// assign do = 8'h00;`
316
317			`endmodule`

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