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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002d.v] - Blame information for rev 25

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Line No. Rev Author Line
1 10 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch<remove>@opencores.org
7
//       ||
8
//
9
// rtf65002.v
10
//  - 32 bit CPU
11
//
12
// This source file is free software: you can redistribute it and/or modify 
13
// it under the terms of the GNU Lesser General Public License as published 
14
// by the Free Software Foundation, either version 3 of the License, or     
15
// (at your option) any later version.                                      
16
//                                                                          
17
// This source file is distributed in the hope that it will be useful,      
18
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
19
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
20
// GNU General Public License for more details.                             
21
//                                                                          
22
// You should have received a copy of the GNU General Public License        
23
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
24
//                                                                          
25
// ============================================================================
26
//
27 5 robfinch
`define TRUE            1'b1
28
`define FALSE           1'b0
29
 
30
`define RST_VECT        34'h3FFFFFFF8
31
`define NMI_VECT        34'h3FFFFFFF4
32
`define IRQ_VECT        34'h3FFFFFFF0
33 13 robfinch
`define BRK_VECTNO      9'd0
34
`define SLP_VECTNO      9'd1
35 21 robfinch
`define BYTE_RST_VECT   34'h00000FFFC
36 5 robfinch
`define BYTE_NMI_VECT   34'h00000FFFA
37
`define BYTE_IRQ_VECT   34'h00000FFFE
38
 
39
`define BRK                     8'h00
40
`define RTI                     8'h40
41
`define RTS                     8'h60
42
`define PHP                     8'h08
43
`define CLC                     8'h18
44
`define PLP                     8'h28
45
`define SEC                     8'h38
46
`define PHA                     8'h48
47
`define CLI                     8'h58
48
`define PLA                     8'h68
49
`define SEI                     8'h78
50
`define DEY                     8'h88
51
`define TYA                     8'h98
52
`define TAY                     8'hA8
53
`define CLV                     8'hB8
54
`define INY                     8'hC8
55
`define CLD                     8'hD8
56
`define INX                     8'hE8
57
`define SED                     8'hF8
58
`define ROR_ACC         8'h6A
59
`define TXA                     8'h8A
60
`define TXS                     8'h9A
61
`define TAX                     8'hAA
62
`define TSX                     8'hBA
63
`define DEX                     8'hCA
64
`define NOP                     8'hEA
65
`define TXY                     8'h9B
66
`define TYX                     8'hBB
67
`define TAS                     8'h1B
68
`define TSA                     8'h3B
69
`define TRS                     8'h8B
70
`define TSR                     8'hAB
71
`define STP                     8'hDB
72
`define NAT                     8'hFB
73
`define EMM                     8'hFB
74
`define INA                     8'h1A
75
`define DEA                     8'h3A
76
 
77
`define RR                      8'h02
78 12 robfinch
`define ADD_RR                  4'd0
79
`define SUB_RR                  4'd1
80
`define CMP_RR                  4'd2
81
`define AND_RR                  4'd3
82
`define EOR_RR                  4'd4
83
`define OR_RR                   4'd5
84
`define MUL_RR                  4'd8
85
`define MULS_RR                 4'd9
86
`define DIV_RR                  4'd10
87
`define DIVS_RR                 4'd11
88
`define MOD_RR                  4'd12
89
`define MODS_RR                 4'd13
90 19 robfinch
`define ASL_RRR                 4'd14
91
`define LSR_RRR                 4'd15
92 12 robfinch
`define LD_RR           8'h7B
93 5 robfinch
 
94
`define ADD_IMM8        8'h65           // 8 bit operand
95
`define ADD_IMM16       8'h79           // 16 bit operand
96
`define ADD_IMM32       8'h69           // 32 bit operand
97
`define ADD_ZPX         8'h75           // there is no ZP mode, use R0 to syntheisze
98
`define ADD_IX          8'h61
99
`define ADD_IY          8'h71
100
`define ADD_ABS         8'h6D
101
`define ADD_ABSX        8'h7D
102
`define ADD_RIND        8'h72
103 23 robfinch
`define ADD_DSP         8'h63
104 5 robfinch
 
105
`define SUB_IMM8        8'hE5
106
`define SUB_IMM16       8'hF9
107
`define SUB_IMM32       8'hE9
108
`define SUB_ZPX         8'hF5
109
`define SUB_IX          8'hE1
110
`define SUB_IY          8'hF1
111
`define SUB_ABS         8'hED
112
`define SUB_ABSX        8'hFD
113
`define SUB_RIND        8'hF2
114 23 robfinch
`define SUB_DSP         8'hE3
115 5 robfinch
 
116
// CMP = SUB r0,....
117
 
118
`define ADC_IMM         8'h69
119
`define ADC_ZP          8'h65
120
`define ADC_ZPX         8'h75
121
`define ADC_IX          8'h61
122
`define ADC_IY          8'h71
123
`define ADC_ABS         8'h6D
124
`define ADC_ABSX        8'h7D
125
`define ADC_ABSY        8'h79
126
`define ADC_I           8'h72
127
 
128
`define SBC_IMM         8'hE9
129
`define SBC_ZP          8'hE5
130
`define SBC_ZPX         8'hF5
131
`define SBC_IX          8'hE1
132
`define SBC_IY          8'hF1
133
`define SBC_ABS         8'hED
134
`define SBC_ABSX        8'hFD
135
`define SBC_ABSY        8'hF9
136
`define SBC_I           8'hF2
137
 
138 19 robfinch
`define CMP_IMM8        8'hC5
139 5 robfinch
`define CMP_IMM32       8'hC9
140
`define CMP_IMM         8'hC9
141
`define CMP_ZP          8'hC5
142
`define CMP_ZPX         8'hD5
143
`define CMP_IX          8'hC1
144
`define CMP_IY          8'hD1
145
`define CMP_ABS         8'hCD
146
`define CMP_ABSX        8'hDD
147
`define CMP_ABSY        8'hD9
148
`define CMP_I           8'hD2
149
 
150
 
151
`define LDA_IMM8        8'hA5
152
`define LDA_IMM16       8'hB9
153
`define LDA_IMM32       8'hA9
154
 
155
`define AND_IMM8        8'h25
156
`define AND_IMM16       8'h39
157
`define AND_IMM32       8'h29
158
`define AND_IMM         8'h29
159
`define AND_ZP          8'h25
160
`define AND_ZPX         8'h35
161
`define AND_IX          8'h21
162
`define AND_IY          8'h31
163
`define AND_ABS         8'h2D
164
`define AND_ABSX        8'h3D
165
`define AND_ABSY        8'h39
166
`define AND_RIND        8'h32
167
`define AND_I           8'h32
168 23 robfinch
`define AND_DSP         8'h23
169 5 robfinch
 
170
`define OR_IMM8         8'h05
171
`define OR_IMM16        8'h19
172
`define OR_IMM32        8'h09
173
`define OR_ZPX          8'h15
174
`define OR_IX           8'h01
175
`define OR_IY           8'h11
176
`define OR_ABS          8'h0D
177
`define OR_ABSX         8'h1D
178
`define OR_RIND         8'h12
179 23 robfinch
`define OR_DSP          8'h03
180 5 robfinch
 
181
`define ORA_IMM         8'h09
182
`define ORA_ZP          8'h05
183
`define ORA_ZPX         8'h15
184
`define ORA_IX          8'h01
185
`define ORA_IY          8'h11
186
`define ORA_ABS         8'h0D
187
`define ORA_ABSX        8'h1D
188
`define ORA_ABSY        8'h19
189
`define ORA_I           8'h12
190
 
191
`define EOR_IMM         8'h49
192
`define EOR_IMM8        8'h45
193
`define EOR_IMM16       8'h59
194
`define EOR_IMM32       8'h49
195
`define EOR_ZP          8'h45
196
`define EOR_ZPX         8'h55
197
`define EOR_IX          8'h41
198
`define EOR_IY          8'h51
199
`define EOR_ABS         8'h4D
200
`define EOR_ABSX        8'h5D
201
`define EOR_ABSY        8'h59
202
`define EOR_RIND        8'h52
203
`define EOR_I           8'h52
204 23 robfinch
`define EOR_DSP         8'h43
205 5 robfinch
 
206
// LD is OR rt,r0,....
207
 
208
`define ST_ZPX          8'h95
209
`define ST_IX           8'h81
210
`define ST_IY           8'h91
211
`define ST_ABS          8'h8D
212
`define ST_ABSX         8'h9D
213
`define ST_RIND         8'h92
214 23 robfinch
`define ST_DSP          8'h83
215 5 robfinch
 
216
`define ORB_ZPX         8'hB5
217
`define ORB_IX          8'hA1
218
`define ORB_IY          8'hB1
219
`define ORB_ABS         8'hAD
220
`define ORB_ABSX        8'hBD
221
 
222
`define STB_ZPX         8'h74
223
`define STB_ABS         8'h9C
224
`define STB_ABSX        8'h9E
225
 
226
 
227
//`define LDB_RIND      8'hB2   // Conflict with LDX #imm16
228
 
229
`define LDA_IMM         8'hA9
230
`define LDA_ZP          8'hA5
231
`define LDA_ZPX         8'hB5
232
`define LDA_IX          8'hA1
233
`define LDA_IY          8'hB1
234
`define LDA_ABS         8'hAD
235
`define LDA_ABSX        8'hBD
236
`define LDA_ABSY        8'hB9
237
`define LDA_I           8'hB2
238
 
239
`define STA_ZP          8'h85
240
`define STA_ZPX         8'h95
241
`define STA_IX          8'h81
242
`define STA_IY          8'h91
243
`define STA_ABS         8'h8D
244
`define STA_ABSX        8'h9D
245
`define STA_ABSY        8'h99
246
`define STA_I           8'h92
247
 
248 19 robfinch
`define ASL_IMM8        8'h24
249 5 robfinch
`define ASL_ACC         8'h0A
250
`define ASL_ZP          8'h06
251
`define ASL_RR          8'h06
252
`define ASL_ZPX         8'h16
253
`define ASL_ABS         8'h0E
254
`define ASL_ABSX        8'h1E
255
 
256
`define ROL_ACC         8'h2A
257
`define ROL_ZP          8'h26
258
`define ROL_RR          8'h26
259
`define ROL_ZPX         8'h36
260
`define ROL_ABS         8'h2E
261
`define ROL_ABSX        8'h3E
262
 
263 19 robfinch
`define LSR_IMM8        8'h34
264 5 robfinch
`define LSR_ACC         8'h4A
265
`define LSR_ZP          8'h46
266
`define LSR_RR          8'h46
267
`define LSR_ZPX         8'h56
268
`define LSR_ABS         8'h4E
269
`define LSR_ABSX        8'h5E
270
 
271
`define ROR_RR          8'h66
272
`define ROR_ZP          8'h66
273
`define ROR_ZPX         8'h76
274
`define ROR_ABS         8'h6E
275
`define ROR_ABSX        8'h7E
276
 
277 12 robfinch
`define DEC_RR          8'hC6
278 5 robfinch
`define DEC_ZP          8'hC6
279
`define DEC_ZPX         8'hD6
280
`define DEC_ABS         8'hCE
281
`define DEC_ABSX        8'hDE
282 12 robfinch
`define INC_RR          8'hE6
283 5 robfinch
`define INC_ZP          8'hE6
284
`define INC_ZPX         8'hF6
285
`define INC_ABS         8'hEE
286
`define INC_ABSX        8'hFE
287
 
288
`define BIT_IMM         8'h89
289
`define BIT_ZP          8'h24
290
`define BIT_ZPX         8'h34
291
`define BIT_ABS         8'h2C
292
`define BIT_ABSX        8'h3C
293
 
294
// CMP = SUB r0,...
295
// BIT = AND r0,...
296
`define BPL                     8'h10
297
`define BVC                     8'h50
298
`define BCC                     8'h90
299
`define BNE                     8'hD0
300
`define BMI                     8'h30
301
`define BVS                     8'h70
302
`define BCS                     8'hB0
303
`define BEQ                     8'hF0
304
`define BRL                     8'h82
305 20 robfinch
`define BRA                     8'h80
306 5 robfinch
 
307
`define JML                     8'h5C
308
`define JMP                     8'h4C
309
`define JMP_IND         8'h6C
310
`define JMP_INDX        8'h7C
311
`define JMP_RIND        8'hD2
312
`define JSR                     8'h20
313
`define JSL                     8'h22
314
`define JSR_INDX        8'hFC
315
`define JSR_RIND        8'hC2
316
`define RTS                     8'h60
317
`define RTL                     8'h6B
318
`define BSR                     8'h62
319
`define NOP                     8'hEA
320
 
321
`define BRK                     8'h00
322
`define PLX                     8'hFA
323
`define PLY                     8'h7A
324
`define PHX                     8'hDA
325
`define PHY                     8'h5A
326
`define WAI                     8'hCB
327
`define PUSH            8'h0B
328
`define POP                     8'h2B
329
 
330
`define LDX_IMM         8'hA2
331
`define LDX_ZP          8'hA6
332
`define LDX_ZPX         8'hB6
333
`define LDX_ZPY         8'hB6
334
`define LDX_ABS         8'hAE
335
`define LDX_ABSY        8'hBE
336
 
337
`define LDX_IMM32       8'hA2
338
`define LDX_IMM16       8'hB2
339
`define LDX_IMM8        8'hA6
340
 
341
`define LDY_IMM         8'hA0
342
`define LDY_ZP          8'hA4
343
`define LDY_ZPX         8'hB4
344
`define LDY_IMM32       8'hA0
345
`define LDY_ABS         8'hAC
346
`define LDY_ABSX        8'hBC
347
 
348
`define STX_ZP          8'h86
349
`define STX_ZPX         8'h96
350
`define STX_ZPY         8'h96
351
`define STX_ABS         8'h8E
352
 
353
`define STY_ZP          8'h84
354
`define STY_ZPX         8'h94
355
`define STY_ABS         8'h8C
356
 
357
`define STZ_ZP          8'h64
358
`define STZ_ZPX         8'h74
359
`define STZ_ABS         8'h9C
360
`define STZ_ABSX        8'h9E
361
 
362
`define CPX_IMM         8'hE0
363
`define CPX_IMM32       8'hE0
364
`define CPX_ZP          8'hE4
365
`define CPX_ZPX         8'hE4
366
`define CPX_ABS         8'hEC
367
`define CPY_IMM         8'hC0
368
`define CPY_IMM32       8'hC0
369
`define CPY_ZP          8'hC4
370
`define CPY_ZPX         8'hC4
371
`define CPY_ABS         8'hCC
372
 
373
`define TRB_ZP          8'h14
374
`define TRB_ZPX         8'h14
375
`define TRB_ABS         8'h1C
376
`define TSB_ZP          8'h04
377
`define TSB_ZPX         8'h04
378
`define TSB_ABS         8'h0C
379
 
380 10 robfinch
`define BAZ                     8'hC1
381
`define BXZ                     8'hD1
382
`define BEQ_RR          8'hE2
383 21 robfinch
`define INT0            8'hDC
384
`define INT1            8'hDD
385 25 robfinch
`define SUB_SP8         8'h85
386
`define SUB_SP16        8'h99
387
`define SUB_SP32        8'h89
388 23 robfinch
`define MVP                     8'h44
389
`define MVN                     8'h54
390 25 robfinch
`define EXEC            8'hEB
391
`define ATNI            8'h4B
392 10 robfinch
 
393 21 robfinch
`define NOTHING         4'd0
394
`define SR_70           4'd1
395
`define SR_310          4'd2
396
`define BYTE_70         4'd3
397
`define WORD_310        4'd4
398
`define PC_70           4'd5
399
`define PC_158          4'd6
400
`define PC_2316         4'd7
401
`define PC_3124         4'd8
402
`define PC_310          4'd9
403
`define WORD_311        4'd10
404
`define IA_310          4'd11
405
`define IA_70           4'd12
406
`define IA_158          4'd13
407
`define BYTE_71         4'd14
408 23 robfinch
`define WORD_312        4'd15
409 21 robfinch
 
410 5 robfinch
module icachemem(wclk, wr, adr, dat, rclk, pc, insn);
411
input wclk;
412
input wr;
413
input [33:0] adr;
414
input [31:0] dat;
415
input rclk;
416
input [31:0] pc;
417 21 robfinch
output reg [63:0] insn;
418 5 robfinch
 
419
wire [63:0] insn0;
420
wire [63:0] insn1;
421
wire [31:0] pcp8 = pc + 32'd8;
422
reg [31:0] rpc;
423
 
424
always @(posedge rclk)
425
        rpc <= pc;
426
 
427
// memL and memH combined allow a 64 bit read
428 10 robfinch
syncRam2kx32_1rw1r ramL0
429 5 robfinch
(
430
        .wrst(1'b0),
431
        .wclk(wclk),
432
        .wce(~adr[2]),
433
        .we(wr),
434
        .wsel(4'hF),
435 10 robfinch
        .wadr(adr[13:3]),
436 5 robfinch
        .i(dat),
437
        .wo(),
438
        .rrst(1'b0),
439
        .rclk(rclk),
440
        .rce(1'b1),
441 10 robfinch
        .radr(pc[13:3]),
442 5 robfinch
        .o(insn0[31:0])
443
);
444
 
445 10 robfinch
syncRam2kx32_1rw1r ramH0
446 5 robfinch
(
447
        .wrst(1'b0),
448
        .wclk(wclk),
449
        .wce(adr[2]),
450
        .we(wr),
451
        .wsel(4'hF),
452 10 robfinch
        .wadr(adr[13:3]),
453 5 robfinch
        .i(dat),
454
        .wo(),
455
        .rrst(1'b0),
456
        .rclk(rclk),
457
        .rce(1'b1),
458 10 robfinch
        .radr(pc[13:3]),
459 5 robfinch
        .o(insn0[63:32])
460
);
461
 
462 10 robfinch
syncRam2kx32_1rw1r ramL1
463 5 robfinch
(
464
        .wrst(1'b0),
465
        .wclk(wclk),
466
        .wce(~adr[2]),
467
        .we(wr),
468
        .wsel(4'hF),
469 10 robfinch
        .wadr(adr[13:3]),
470 5 robfinch
        .i(dat),
471
        .wo(),
472
        .rrst(1'b0),
473
        .rclk(rclk),
474
        .rce(1'b1),
475 10 robfinch
        .radr(pcp8[13:3]),
476 5 robfinch
        .o(insn1[31:0])
477
);
478
 
479 10 robfinch
syncRam2kx32_1rw1r ramH1
480 5 robfinch
(
481
        .wrst(1'b0),
482
        .wclk(wclk),
483
        .wce(adr[2]),
484
        .we(wr),
485
        .wsel(4'hF),
486 10 robfinch
        .wadr(adr[13:3]),
487 5 robfinch
        .i(dat),
488
        .wo(),
489
        .rrst(1'b0),
490
        .rclk(rclk),
491
        .rce(1'b1),
492 10 robfinch
        .radr(pcp8[13:3]),
493 5 robfinch
        .o(insn1[63:32])
494
);
495
 
496
always @(rpc or insn0 or insn1)
497
case(rpc[2:0])
498 21 robfinch
3'd0:   insn <= insn0[63:0];
499
3'd1:   insn <= {insn1[7:0],insn0[63:8]};
500
3'd2:   insn <= {insn1[15:0],insn0[63:16]};
501
3'd3:   insn <= {insn1[23:0],insn0[63:24]};
502
3'd4:   insn <= {insn1[31:0],insn0[63:32]};
503
3'd5:   insn <= {insn1[39:0],insn0[63:40]};
504
3'd6:   insn <= {insn1[47:0],insn0[63:48]};
505
3'd7:   insn <= {insn1[55:0],insn0[63:56]};
506 5 robfinch
endcase
507
endmodule
508
 
509
module tagmem(wclk, wr, adr, rclk, pc, hit0, hit1);
510
input wclk;
511
input wr;
512
input [33:0] adr;
513
input rclk;
514
input [31:0] pc;
515
output hit0;
516
output hit1;
517
 
518
wire [31:0] pcp8 = pc + 32'd8;
519
wire [31:0] tag0;
520
wire [31:0] tag1;
521
reg [31:0] rpc;
522
reg [31:0] rpcp8;
523
 
524
always @(posedge rclk)
525
        rpc <= pc;
526
always @(posedge rclk)
527
        rpcp8 <= pcp8;
528
 
529 10 robfinch
syncRam1kx32_1rw1r ram0 (
530 5 robfinch
        .wrst(1'b0),
531
        .wclk(wclk),
532
        .wce(adr[3:2]==2'b11),
533
        .we(wr),
534 10 robfinch
        .wsel(4'hF),
535
        .wadr(adr[13:4]),
536 5 robfinch
        .i(adr[31:0]),
537
        .wo(),
538
 
539 10 robfinch
        .rrst(1'b0),
540
        .rclk(rclk),
541
        .rce(1'b1),
542
        .radr(pc[13:4]),
543
        .o(tag0)
544
);
545 5 robfinch
 
546 10 robfinch
syncRam1kx32_1rw1r ram1 (
547
        .wrst(1'b0),
548
        .wclk(wclk),
549
        .wce(adr[3:2]==2'b11),
550
        .we(wr),
551
        .wsel(4'hF),
552
        .wadr(adr[13:4]),
553
        .i(adr[31:0]),
554
        .wo(),
555
 
556
        .rrst(1'b0),
557
        .rclk(rclk),
558
        .rce(1'b1),
559
        .radr(pcp8[13:4]),
560
        .o(tag1)
561 5 robfinch
);
562
 
563 10 robfinch
assign hit0 = tag0[31:14]==rpc[31:14] && tag0[0];
564
assign hit1 = tag1[31:14]==rpcp8[31:14] && tag1[0];
565 5 robfinch
 
566
endmodule
567
 
568
module dcachemem(wclk, wr, sel, wadr, wdat, rclk, radr, rdat);
569
input wclk;
570
input wr;
571
input [3:0] sel;
572
input [31:0] wadr;
573
input [31:0] wdat;
574
input rclk;
575
input [31:0] radr;
576
output [31:0] rdat;
577
 
578
syncRam2kx32_1rw1r ram0 (
579
        .wrst(1'b0),
580
        .wclk(wclk),
581
        .wce(1'b1),
582
        .we(wr),
583
        .wsel(sel),
584
        .wadr(wadr[10:0]),
585
        .i(wdat),
586
        .wo(),
587
        .rrst(1'b0),
588
        .rclk(rclk),
589
        .rce(1'b1),
590
        .radr(radr[10:0]),
591
        .o(rdat)
592
);
593
 
594
endmodule
595
 
596
module dtagmem(wclk, wr, wadr, rclk, radr, hit);
597
input wclk;
598
input wr;
599
input [31:0] wadr;
600
input rclk;
601
input [31:0] radr;
602
output hit;
603
 
604
reg [31:0] rradr;
605
wire [31:0] tag;
606
 
607
syncRam512x32_1rw1r u1
608
        (
609
                .wrst(1'b0),
610
                .wclk(wclk),
611
                .wce(wadr[1:0]==2'b11),
612
                .we(wr),
613
                .wadr(wadr[10:2]),
614
                .i(wadr),
615
                .wo(),
616
                .rrst(1'b0),
617
                .rclk(rclk),
618
                .rce(1'b1),
619
                .radr(radr[10:2]),
620
                .o(tag)
621
        );
622
 
623
 
624
always @(rclk)
625
        rradr <= radr;
626
 
627
assign hit = tag[31:11]==rradr[31:11];
628
 
629
endmodule
630
 
631
module overflow(op, a, b, s, v);
632
 
633
input op;       // 0=add,1=sub
634
input a;
635
input b;
636
input s;        // sum
637
output v;
638
 
639
// Overflow:
640
// Add: the signs of the inputs are the same, and the sign of the
641
// sum is different
642
// Sub: the signs of the inputs are different, and the sign of
643
// the sum is the same as B
644
assign v = (op ^ s ^ b) & (~op ^ a ^ b);
645
 
646 12 robfinch
endmodule
647 25 robfinch
/*
648
// This table being setup to set the pc increment. It should synthesize to a ROM.
649
module m_pcinc(opcode,inc);
650
input [7:0] opcode;
651
output [3:0] inc;
652 5 robfinch
 
653 25 robfinch
always @(opcode)
654
if (em)
655
else
656
case(opcode)
657
`BRK:   inc <= 4'd1;
658
`BPL,`BMI,`BCS,`BCC,`BVS,`BVC,`BEQ,`BNE,`BRA:   inc <= 4'd2;
659
`BRL: inc <= 4'd3;
660
`CLC,`SEC,`CLD,`SED,`CLV,`CLI,`SEI:     inc <= 4'd1;
661
`TAS,`TSA,`TAY,`TYA,`TAX,`TXA,`TSX,`TXS,`TYX,`TXY:      inc <= 4'd1;
662
`TRS,`TSR: inc <= 4'd2;
663
`INY,`DEY,`INX,`DEX,`INA,`DEA: inc <= 4'd1;
664
`EMM: inc <= 4'd1;
665
`PHA,`PHX,`PHY,`PHP: inc <= 4'd1;
666
`PLA,`PLX,`PLY,`PLP: inc <= 4'd1;
667
`PUSH,`POP: inc <= 4'd2;
668
`STP,`WAI: inc <= 4'd1;
669
`JMP,`JSR: inc <= 4'd3;
670
`JML,`JSL,`JMP_IND,`JMP_INDX,`JSR_INDX: inc <= 4'd5;
671
`JMP_RIND,`JSR_RIND: inc <= 4'd2;
672
`RTS,`RTI,`RTL: inc <= 4'd1;
673
`NOP: inc <= 4'd1;
674
`BSR: inc <= 4'd3;
675
`RR: inc <= 4'd3;
676
`LD_RR: inc <= 4'd2;
677
`ADD_IMM8,`SUB_IMM8,`AND_IMM8,`OR_IMM8,`EOR_IMM8:       inc <= 4'd2;
678
`ADD_IMM16,`SUB_IMM16,`AND_IMM16,`OR_IMM16,`EOR_IMM16:  inc <= 4'd3;
679
`ADD_IMM32,`SUB_IMM32,`AND_IMM32,`OR_IMM32,`EOR_IMM32:  inc <= 4'd5;
680
`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`OR_ZPX,`EOR_ZPX: inc <= 4'd4;
681
`ADD_IX,`SUB_IX,`AND_IX,`OR_IX,`EOR_IX: inc <= 4'd4;
682
`ADD_IY,`SUB_IY,`AND_IY,`OR_IY,`EOR_IY: inc <= 4'd4;
683
`ADD_ABS,`SUB_ABS,`AND_ABS,`OR_ABS,`EOR_ABS: inc <= 4'd6;
684
`ADD_ABSX,`SUB_ABSX,`AND_ABSX,`OR_ABSX,`EOR_ABSX: inc <= 4'd7;
685
`ADD_RIND,`SUB_RIND,`AND_RIND,`OR_RIND,`EOR_RIND: inc <= 4'd2;
686
`ADD_DSP,`SUB_DSP,`AND_DSP,`OR_DSP,`EOR_DSP: inc <= 4'd3;
687
endcase
688
endmodule*/
689 12 robfinch
 
690 25 robfinch
 
691
 
692 21 robfinch
module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o);
693 5 robfinch
parameter IDLE = 3'd0;
694
parameter LOAD_DCACHE = 3'd1;
695
parameter LOAD_ICACHE = 3'd2;
696
parameter LOAD_IBUF1 = 3'd3;
697
parameter LOAD_IBUF2 = 3'd4;
698
parameter LOAD_IBUF3 = 3'd5;
699 10 robfinch
parameter RESET1 = 7'd0;
700 5 robfinch
parameter IFETCH = 7'd1;
701
parameter JMP_IND1 = 7'd2;
702
parameter JMP_IND2 = 7'd3;
703
parameter DECODE = 7'd4;
704
parameter STORE1 = 7'd5;
705
parameter STORE2 = 7'd6;
706
parameter LOAD1 = 7'd7;
707
parameter LOAD2 = 7'd8;
708
parameter IRQ1 = 7'd9;
709
parameter IRQ2 = 7'd10;
710
parameter IRQ3 = 7'd11;
711
parameter CALC = 7'd12;
712
parameter JSR1 = 7'd13;
713
parameter JSR_INDX1 = 7'd14;
714
parameter JSR161 = 7'd15;
715
parameter RTS1 = 7'd16;
716
parameter IX1 = 7'd18;
717
parameter IX2 = 7'd19;
718
parameter IX3 = 7'd20;
719
parameter IX4 = 7'd21;
720
parameter IY1 = 7'd22;
721
parameter IY2 = 7'd23;
722
parameter IY3 = 7'd24;
723
parameter BSR1 = 7'd32;
724
parameter BYTE_IX5 = 7'd37;
725
parameter BYTE_IY5 = 7'd42;
726
parameter BYTE_JSR1 = 7'd46;
727
parameter BYTE_JSR2 = 7'd47;
728
parameter BYTE_JSR3 = 7'd48;
729
parameter BYTE_IRQ1 = 7'd49;
730
parameter BYTE_IRQ2 = 7'd50;
731
parameter BYTE_IRQ3 = 7'd51;
732
parameter BYTE_IRQ4 = 7'd52;
733
parameter BYTE_IRQ5 = 7'd53;
734
parameter BYTE_IRQ6 = 7'd54;
735
parameter BYTE_IRQ7 = 7'd55;
736
parameter BYTE_IRQ8 = 7'd56;
737
parameter BYTE_IRQ9 = 7'd57;
738
parameter BYTE_JMP_IND1 = 7'd58;
739
parameter BYTE_JMP_IND2 = 7'd59;
740
parameter BYTE_JMP_IND3 = 7'd60;
741
parameter BYTE_JMP_IND4 = 7'd61;
742
parameter BYTE_JSR_INDX1 = 7'd62;
743
parameter BYTE_JSR_INDX2 = 7'd63;
744
parameter BYTE_JSR_INDX3 = 7'd64;
745
parameter RTI1 = 7'd65;
746
parameter RTI2 = 7'd66;
747
parameter RTI3 = 7'd67;
748
parameter RTI4 = 7'd68;
749
parameter BYTE_RTS1 = 7'd69;
750
parameter BYTE_RTS2 = 7'd70;
751
parameter BYTE_RTS3 = 7'd71;
752
parameter BYTE_RTS4 = 7'd72;
753
parameter BYTE_RTS5 = 7'd73;
754
parameter BYTE_RTS6 = 7'd74;
755
parameter BYTE_RTS7 = 7'd75;
756
parameter BYTE_RTS8 = 7'd76;
757
parameter BYTE_RTS9 = 7'd77;
758
parameter BYTE_RTI1 = 7'd78;
759
parameter BYTE_RTI2 = 7'd79;
760
parameter BYTE_RTI3 = 7'd80;
761
parameter BYTE_RTI4 = 7'd81;
762
parameter BYTE_RTI5 = 7'd82;
763
parameter BYTE_RTI6 = 7'd83;
764
parameter BYTE_RTI7 = 7'd84;
765
parameter BYTE_RTI8 = 7'd85;
766
parameter BYTE_RTI9 = 7'd86;
767
parameter BYTE_RTI10 = 7'd87;
768
parameter BYTE_JSL1 = 7'd88;
769
parameter BYTE_JSL2 = 7'd89;
770
parameter BYTE_JSL3 = 7'd90;
771
parameter BYTE_JSL4 = 7'd91;
772
parameter BYTE_JSL5 = 7'd92;
773
parameter BYTE_JSL6 = 7'd93;
774
parameter BYTE_JSL7 = 7'd94;
775
parameter BYTE_PLP1 = 7'd95;
776
parameter BYTE_PLP2 = 7'd96;
777
parameter BYTE_PLA1 = 7'd97;
778
parameter BYTE_PLA2 = 7'd98;
779 10 robfinch
parameter WAIT_DHIT = 7'd99;
780
parameter RESET2 = 7'd100;
781 12 robfinch
parameter MULDIV1 = 7'd101;
782
parameter MULDIV2 = 7'd102;
783 20 robfinch
parameter BYTE_DECODE = 7'd103;
784
parameter BYTE_CALC = 7'd104;
785 21 robfinch
parameter BUS_ERROR = 7'd105;
786
parameter INSN_BUS_ERROR = 7'd106;
787
parameter LOAD_MAC1 = 7'd107;
788
parameter LOAD_MAC2 = 7'd108;
789 23 robfinch
parameter MVN1 = 7'd109;
790
parameter MVN2 = 7'd110;
791
parameter MVN3 = 7'd111;
792
parameter MVP1 = 7'd112;
793
parameter MVP2 = 7'd113;
794 5 robfinch
 
795 21 robfinch
input rst_md;           // reset mode, 1=emulation mode, 0=native mode
796 5 robfinch
input rst_i;
797
input clk_i;
798
input nmi_i;
799
input irq_i;
800 13 robfinch
input [8:0] irq_vect;
801 5 robfinch
output reg [1:0] bte_o;
802
output reg [2:0] cti_o;
803
output reg [5:0] bl_o;
804
output reg lock_o;
805
output reg cyc_o;
806
output reg stb_o;
807
input ack_i;
808 21 robfinch
input err_i;
809 5 robfinch
output reg we_o;
810
output reg [3:0] sel_o;
811
output reg [33:0] adr_o;
812
input [31:0] dat_i;
813
output reg [31:0] dat_o;
814
 
815
reg [6:0] state;
816 10 robfinch
reg [6:0] retstate;
817 5 robfinch
reg [2:0] cstate;
818 21 robfinch
wire [63:0] insn;
819
reg [63:0] ibuf;
820 5 robfinch
reg [31:0] bufadr;
821 25 robfinch
reg [63:0] exbuf;
822 5 robfinch
 
823
reg cf,nf,zf,vf,bf,im,df,em;
824
reg em1;
825 10 robfinch
reg gie;
826 25 robfinch
reg hwi;        // hardware interrupt indicator
827 5 robfinch
reg nmoi;       // native mode on interrupt
828
wire [31:0] sr = {nf,vf,em,24'b0,bf,df,im,zf,cf};
829
wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};
830
reg nmi1,nmi_edge;
831
reg wai;
832
reg [31:0] acc;
833
reg [31:0] x;
834
reg [31:0] y;
835
reg [7:0] sp;
836 13 robfinch
reg [31:0] spage;        // stack page
837 5 robfinch
wire [7:0] acc8 = acc[7:0];
838
wire [7:0] x8 = x[7:0];
839
wire [7:0] y8 = y[7:0];
840
reg [31:0] isp;          // interrupt stack pointer
841 12 robfinch
wire [63:0] prod;
842
wire [31:0] q,r;
843
reg [31:0] tick;
844 5 robfinch
wire [7:0] sp_dec = sp - 8'd1;
845
wire [7:0] sp_inc = sp + 8'd1;
846
wire [31:0] isp_dec = isp - 32'd1;
847
wire [31:0] isp_inc = isp + 32'd1;
848 25 robfinch
reg [3:0] suppress_pcinc;
849 5 robfinch
reg [31:0] pc;
850 23 robfinch
reg [31:0] opc;
851 25 robfinch
wire [31:0] pcp1 = pc + (32'd1 & suppress_pcinc);
852
wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc);
853
wire [31:0] pcp3 = pc + (32'd3 & suppress_pcinc);
854
wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc);
855
wire [31:0] pcp5 = pc + (32'd5 & suppress_pcinc);
856
wire [31:0] pcp6 = pc + (32'd6 & suppress_pcinc);
857
wire [31:0] pcp7 = pc + (32'd7 & suppress_pcinc);
858
wire [31:0] pcp8 = pc + (32'd8 & suppress_pcinc);
859 13 robfinch
reg [31:0] dp;           // 32 bit mode direct page register
860
reg [31:0] dp8;          // 8 bit mode direct page register
861
reg [31:0] abs8; // 8 bit mode absolute address register
862
reg [31:0] vbr;          // vector table base register
863 5 robfinch
wire bhit=pc==bufadr;
864
reg [31:0] regfile [15:0];
865 21 robfinch
reg [63:0] ir;
866 5 robfinch
wire [3:0] Ra = ir[11:8];
867
wire [3:0] Rb = ir[15:12];
868
reg [31:0] rfoa;
869
reg [31:0] rfob;
870
always @(Ra or x or y or acc)
871
case(Ra)
872
4'h0:   rfoa <= 32'd0;
873
4'h1:   rfoa <= acc;
874
4'h2:   rfoa <= x;
875
4'h3:   rfoa <= y;
876
default:        rfoa <= regfile[Ra];
877
endcase
878
always @(Rb or x or y or acc)
879
case(Rb)
880
4'h0:   rfob <= 32'd0;
881
4'h1:   rfob <= acc;
882
4'h2:   rfob <= x;
883
4'h3:   rfob <= y;
884
default:        rfob <= regfile[Rb];
885
endcase
886
reg [3:0] Rt;
887
reg [33:0] ea;
888
reg first_ifetch;
889 12 robfinch
reg [31:0] lfsr;
890
wire lfsr_fb;
891
xnor(lfsr_fb,lfsr[0],lfsr[1],lfsr[21],lfsr[31]);
892 5 robfinch
reg [31:0] a, b;
893 19 robfinch
wire [31:0] shlo = a << b[4:0];
894
wire [31:0] shro = a >> b[4:0];
895 5 robfinch
reg [7:0] b8;
896
reg [32:0] res;
897
reg [8:0] res8;
898
wire resv8,resv32;
899
wire resc8 = res8[8];
900
wire resc32 = res[32];
901
wire resz8 = res8[7:0]==8'h00;
902
wire resz32 = res[31:0]==32'd0;
903
wire resn8 = res8[7];
904
wire resn32 = res[31];
905
wire resn = em ? res8[7] : res[31];
906
wire resz = em ? res8[7:0]==8'h00 : res[31:0]==32'd0;
907
wire resc = em ? res8[8] : res[32];
908
wire resv = em ? resv8 : resv32;
909
 
910
reg [31:0] vect;
911
reg [31:0] ia;                   // temporary reg to hold indirect address
912 20 robfinch
wire [31:0] iapy8 = abs8 + ia + y[7:0];
913 5 robfinch
reg isInsnCacheLoad;
914
reg isDataCacheLoad;
915 10 robfinch
reg isCacheReset;
916 5 robfinch
wire hit0,hit1;
917
wire dhit;
918 10 robfinch
reg write_allocate;
919 5 robfinch
reg wr;
920
reg [3:0] wrsel;
921
reg [31:0] radr;
922
reg [1:0] radr2LSB;
923
wire [33:0] radr34 = {radr,radr2LSB};
924
wire [33:0] radr34p1 = radr34 + 34'd1;
925
reg [31:0] wadr;
926
reg [1:0] wadr2LSB;
927
reg [31:0] wdat;
928
wire [31:0] rdat;
929 21 robfinch
reg [3:0] load_what;
930
reg [3:0] store_what;
931 23 robfinch
reg [31:0] derr_address;
932 5 robfinch
reg imiss;
933
reg dmiss;
934
reg icacheOn,dcacheOn;
935 20 robfinch
wire unCachedData = radr[31:20]==12'hFFD || !dcacheOn;  // I/O area is uncached
936
wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn;              // The lowest 8kB is uncached.
937 5 robfinch
 
938
wire isSub = ir[7:0]==`SUB_ZPX || ir[7:0]==`SUB_IX || ir[7:0]==`SUB_IY ||
939
                         ir[7:0]==`SUB_ABS || ir[7:0]==`SUB_ABSX || ir[7:0]==`SUB_IMM8 || ir[7:0]==`SUB_IMM16 || ir[7:0]==`SUB_IMM32;
940
wire isSub8 = ir[7:0]==`SBC_ZP || ir[7:0]==`SBC_ZPX || ir[7:0]==`SBC_IX || ir[7:0]==`SBC_IY || ir[7:0]==`SBC_I ||
941
                         ir[7:0]==`SBC_ABS || ir[7:0]==`SBC_ABSX || ir[7:0]==`SBC_ABSY || ir[7:0]==`SBC_IMM;
942
wire isCmp = ir[7:0]==`CPX_ZPX || ir[7:0]==`CPX_ABS || ir[7:0]==`CPX_IMM32 ||
943
                         ir[7:0]==`CPY_ZPX || ir[7:0]==`CPY_ABS || ir[7:0]==`CPY_IMM32;
944
wire isRMW32 =
945
                         ir[7:0]==`ASL_ZPX || ir[7:0]==`ROL_ZPX || ir[7:0]==`LSR_ZPX || ir[7:0]==`ROR_ZPX || ir[7:0]==`INC_ZPX || ir[7:0]==`DEC_ZPX ||
946
                         ir[7:0]==`ASL_ABS || ir[7:0]==`ROL_ABS || ir[7:0]==`LSR_ABS || ir[7:0]==`ROR_ABS || ir[7:0]==`INC_ABS || ir[7:0]==`DEC_ABS ||
947
                         ir[7:0]==`ASL_ABSX || ir[7:0]==`ROL_ABSX || ir[7:0]==`LSR_ABSX || ir[7:0]==`ROR_ABSX || ir[7:0]==`INC_ABSX || ir[7:0]==`DEC_ABSX ||
948
                         ir[7:0]==`TRB_ZP || ir[7:0]==`TRB_ZPX || ir[7:0]==`TRB_ABS || ir[7:0]==`TSB_ZP || ir[7:0]==`TSB_ZPX || ir[7:0]==`TSB_ABS;
949
                         ;
950
wire isRMW8 =
951
                         ir[7:0]==`ASL_ZP || ir[7:0]==`ROL_ZP || ir[7:0]==`LSR_ZP || ir[7:0]==`ROR_ZP || ir[7:0]==`INC_ZP || ir[7:0]==`DEC_ZP ||
952
                         ir[7:0]==`ASL_ZPX || ir[7:0]==`ROL_ZPX || ir[7:0]==`LSR_ZPX || ir[7:0]==`ROR_ZPX || ir[7:0]==`INC_ZPX || ir[7:0]==`DEC_ZPX ||
953
                         ir[7:0]==`ASL_ABS || ir[7:0]==`ROL_ABS || ir[7:0]==`LSR_ABS || ir[7:0]==`ROR_ABS || ir[7:0]==`INC_ABS || ir[7:0]==`DEC_ABS ||
954
                         ir[7:0]==`ASL_ABSX || ir[7:0]==`ROL_ABSX || ir[7:0]==`LSR_ABSX || ir[7:0]==`ROR_ABSX || ir[7:0]==`INC_ABSX || ir[7:0]==`DEC_ABSX ||
955
                         ir[7:0]==`TRB_ZP || ir[7:0]==`TRB_ZPX || ir[7:0]==`TRB_ABS || ir[7:0]==`TSB_ZP || ir[7:0]==`TSB_ZPX || ir[7:0]==`TSB_ABS;
956
                         ;
957
wire isRMW = em ? isRMW8 : isRMW32;
958
wire isOrb = ir[7:0]==`ORB_ZPX || ir[7:0]==`ORB_IX || ir[7:0]==`ORB_IY || ir[7:0]==`ORB_ABS || ir[7:0]==`ORB_ABSX;
959
wire isStb = ir[7:0]==`STB_ZPX || ir[7:0]==`STB_ABS || ir[7:0]==`STB_ABSX;
960 21 robfinch
wire isRTI = ir[7:0]==`RTI;
961
wire isRTL = ir[7:0]==`RTL;
962
wire isRTS = ir[7:0]==`RTS;
963 23 robfinch
wire isMove = ir[7:0]==`MVP || ir[7:0]==`MVN;
964 25 robfinch
wire isExec = ir[7:0]==`EXEC;
965
wire isAtni = ir[7:0]==`ATNI;
966 12 robfinch
wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
967
wire md_done;
968
wire clk;
969 21 robfinch
reg isIY;
970 12 robfinch
 
971
mult_div umd1
972
(
973
        .rst(rst),
974
        .clk(clk),
975
        .ld(ld_muldiv),
976
        .op(ir[23:20]),
977
        .a(rfoa),
978
        .b(rfob),
979
        .p(prod),
980
        .q(q),
981
        .r(r),
982
        .done(md_done)
983
);
984
 
985 5 robfinch
icachemem icm0 (
986 12 robfinch
        .wclk(clk),
987 5 robfinch
        .wr(ack_i & isInsnCacheLoad),
988
        .adr(adr_o),
989
        .dat(dat_i),
990
        .rclk(~clk_i),
991
        .pc(pc),
992
        .insn(insn)
993
);
994
 
995
tagmem tgm0 (
996 12 robfinch
        .wclk(clk),
997 10 robfinch
        .wr((ack_i & isInsnCacheLoad)|isCacheReset),
998
        .adr({adr_o[31:1],!isCacheReset}),
999 5 robfinch
        .rclk(~clk_i),
1000
        .pc(pc),
1001
        .hit0(hit0),
1002
        .hit1(hit1)
1003
);
1004
 
1005
wire ihit = (hit0 & hit1);//(pc[2:0] > 3'd1 ? hit1 : 1'b1));
1006
 
1007
dcachemem dcm0 (
1008 12 robfinch
        .wclk(clk),
1009 5 robfinch
        .wr(wr | (ack_i & isDataCacheLoad)),
1010
        .sel(wr ? wrsel : sel_o),
1011
        .wadr(wr ? wadr : adr_o[33:2]),
1012
        .wdat(wr ? wdat : dat_i),
1013
        .rclk(~clk_i),
1014
        .radr(radr),
1015
        .rdat(rdat)
1016
);
1017
 
1018
dtagmem dtm0 (
1019 12 robfinch
        .wclk(clk),
1020 5 robfinch
        .wr(wr | (ack_i & isDataCacheLoad)),
1021
        .wadr(wr ? wadr : adr_o[33:2]),
1022
        .rclk(~clk_i),
1023
        .radr(radr),
1024
        .hit(dhit)
1025
);
1026
 
1027
overflow uovr1 (
1028
        .op(isSub),
1029
        .a(a[31]),
1030
        .b(b[31]),
1031
        .s(res[31]),
1032
        .v(resv32)
1033
);
1034
 
1035
overflow uovr2 (
1036
        .op(isSub8),
1037
        .a(acc8[7]),
1038
        .b(b8[7]),
1039
        .s(res8[7]),
1040
        .v(resv8)
1041
);
1042
 
1043
wire [7:0] bcaio;
1044
wire [7:0] bcao;
1045
wire [7:0] bcsio;
1046
wire [7:0] bcso;
1047
wire bcaico,bcaco,bcsico,bcsco;
1048
 
1049
BCDAdd ubcdai1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcaio),.c(bcaico));
1050
BCDAdd ubcda2 (.ci(cf),.a(acc8),.b(b8),.o(bcao),.c(bcaco));
1051
BCDSub ubcdsi1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcsio),.c(bcsico));
1052
BCDSub ubcds2 (.ci(cf),.a(acc8),.b(b8),.o(bcso),.c(bcsco));
1053
 
1054
reg [7:0] dati;
1055
always @(radr2LSB or dat_i)
1056
case(radr2LSB)
1057
2'd0:   dati <= dat_i[7:0];
1058
2'd1:   dati <= dat_i[15:8];
1059
2'd2:   dati <= dat_i[23:16];
1060
2'd3:   dati <= dat_i[31:24];
1061
endcase
1062
reg [7:0] rdat8;
1063
always @(radr2LSB or rdat)
1064
case(radr2LSB)
1065
2'd0:   rdat8 <= rdat[7:0];
1066
2'd1:   rdat8 <= rdat[15:8];
1067
2'd2:   rdat8 <= rdat[23:16];
1068
2'd3:   rdat8 <= rdat[31:24];
1069
endcase
1070
 
1071
reg takb;
1072
always @(ir or cf or vf or nf or zf)
1073
case(ir[7:0])
1074
`BEQ:   takb <= zf;
1075
`BNE:   takb <= !zf;
1076
`BPL:   takb <= !nf;
1077
`BMI:   takb <= nf;
1078
`BCS:   takb <= cf;
1079
`BCC:   takb <= !cf;
1080
`BVS:   takb <= vf;
1081
`BVC:   takb <= !vf;
1082
`BRA:   takb <= 1'b1;
1083
`BRL:   takb <= 1'b1;
1084 10 robfinch
//`BAZ: takb <= acc8==8'h00;
1085
//`BXZ: takb <= x8==8'h00;
1086 5 robfinch
default:        takb <= 1'b0;
1087
endcase
1088
 
1089 13 robfinch
wire [31:0] zp_address = dp8 + ir[15:8];
1090 25 robfinch
wire [31:0] zpx_address = zp_address + x8;
1091
wire [31:0] zpy_address = zp_address + y8;
1092 13 robfinch
wire [31:0] abs_address = abs8 + {16'h0,ir[23:8]};
1093 25 robfinch
wire [31:0] absx_address = abs8 + {16'h0,ir[23:8] + {8'h0,x8}};  // simulates 64k bank wrap-around
1094 13 robfinch
wire [31:0] absy_address = abs8 + {16'h0,ir[23:8] + {8'h0,y8}};
1095 5 robfinch
wire [31:0] zpx32xy_address = dp + ir[23:12] + rfoa;
1096
wire [31:0] absx32xy_address = ir[47:16] + rfob;
1097
wire [31:0] zpx32_address = dp + ir[31:20] + rfob;
1098
wire [31:0] absx32_address = ir[55:24] + rfob;
1099
 
1100
//-----------------------------------------------------------------------------
1101
// Clock control
1102
// - reset or NMI reenables the clock
1103
// - this circuit must be under the clk_i domain
1104
//-----------------------------------------------------------------------------
1105
//
1106
reg cpu_clk_en;
1107
reg clk_en;
1108
BUFGCE u20 (.CE(cpu_clk_en), .I(clk_i), .O(clk) );
1109
 
1110
always @(posedge clk_i)
1111
if (rst_i) begin
1112
        cpu_clk_en <= 1'b1;
1113
        nmi1 <= 1'b0;
1114
end
1115
else begin
1116
        nmi1 <= nmi_i;
1117
        if (nmi_i)
1118
                cpu_clk_en <= 1'b1;
1119
        else
1120
                cpu_clk_en <= clk_en;
1121
end
1122
 
1123
always @(posedge clk)
1124
if (rst_i) begin
1125
        bte_o <= 2'b00;
1126
        cti_o <= 3'b000;
1127
        bl_o <= 6'd0;
1128
        cyc_o <= 1'b0;
1129
        stb_o <= 1'b0;
1130
        we_o <= 1'b0;
1131
        sel_o <= 4'h0;
1132
        adr_o <= 34'd0;
1133
        dat_o <= 32'd0;
1134
        nmi_edge <= 1'b0;
1135
        wai <= 1'b0;
1136
        first_ifetch <= `TRUE;
1137
        wr <= 1'b0;
1138
        cf <= 1'b0;
1139
        ir <= 56'hEAEAEAEAEAEAEA;
1140
        imiss <= `FALSE;
1141
        dmiss <= `FALSE;
1142
        dcacheOn <= 1'b0;
1143
        icacheOn <= 1'b1;
1144 10 robfinch
        write_allocate <= 1'b0;
1145 5 robfinch
        nmoi <= 1'b1;
1146 10 robfinch
        state <= RESET1;
1147 5 robfinch
        cstate <= IDLE;
1148 21 robfinch
        if (rst_md) begin
1149
                pc <= 32'h0000FFF0;             // set high-order pc to zero
1150
                vect <= `BYTE_RST_VECT;
1151
                em <= 1'b1;
1152
        end
1153
        else begin
1154
                vect <= `RST_VECT;
1155
                em <= 1'b0;
1156
                pc <= 32'hFFFFFFF0;
1157
        end
1158 25 robfinch
        suppress_pcinc <= 4'hF;
1159
        exbuf <= 64'd0;
1160 13 robfinch
        spage <= 32'h00000100;
1161 5 robfinch
        bufadr <= 32'd0;
1162
        dp <= 32'd0;
1163 13 robfinch
        dp8 <= 32'd0;
1164
        abs8 <= 32'd0;
1165 5 robfinch
        clk_en <= 1'b1;
1166 10 robfinch
        isCacheReset <= `TRUE;
1167
        gie <= 1'b0;
1168 12 robfinch
        tick <= 32'd0;
1169 21 robfinch
        isIY <= 1'b0;
1170 5 robfinch
end
1171
else begin
1172 12 robfinch
tick <= tick + 32'd1;
1173 5 robfinch
wr <= 1'b0;
1174
if (nmi_i & !nmi1)
1175
        nmi_edge <= 1'b1;
1176
if (nmi_i|nmi1)
1177
        clk_en <= 1'b1;
1178
case(state)
1179 10 robfinch
RESET1:
1180 5 robfinch
        begin
1181 10 robfinch
                adr_o <= adr_o + 32'd4;
1182
                if (adr_o[13:4]==10'h3FF) begin
1183
                        state <= RESET2;
1184
                        isCacheReset <= `FALSE;
1185
                end
1186
        end
1187
RESET2:
1188
        begin
1189 5 robfinch
                radr <= vect[31:2];
1190 21 robfinch
                radr2LSB <= vect[1:0];
1191
                load_what <= em ? `PC_70 : `PC_310;
1192
                state <= LOAD_MAC1;
1193 5 robfinch
        end
1194
 
1195 20 robfinch
`include "ifetch.v"
1196
`include "decode.v"
1197
`include "byte_decode.v"
1198 10 robfinch
 
1199 21 robfinch
`include "load_mac.v"
1200 20 robfinch
`include "store.v"
1201 10 robfinch
 
1202
WAIT_DHIT:
1203
        if (dhit)
1204
                state <= retstate;
1205 5 robfinch
 
1206 20 robfinch
`include "byte_calc.v"
1207 5 robfinch
`include "calc.v"
1208 20 robfinch
`include "byte_jsr.v"
1209
`include "byte_jsl.v"
1210 5 robfinch
 
1211
JSR1:
1212
        if (ack_i) begin
1213 10 robfinch
                state <= IFETCH;
1214
                retstate <= IFETCH;
1215 5 robfinch
                cyc_o <= 1'b0;
1216
                stb_o <= 1'b0;
1217
                we_o <= 1'b0;
1218
                sel_o <= 4'h0;
1219
                adr_o <= 34'd0;
1220
                dat_o <= 32'd0;
1221
                pc <= vect;
1222
                isp <= isp_dec;
1223
                if (dhit) begin
1224
                        wrsel <= sel_o;
1225
                        wr <= 1'b1;
1226
                end
1227 10 robfinch
                else if (write_allocate) begin
1228
                        state <= WAIT_DHIT;
1229
                        dmiss <= `TRUE;
1230
                end
1231 5 robfinch
        end
1232
 
1233
JSR_INDX1:
1234
        if (ack_i) begin
1235 21 robfinch
                load_what <= `PC_310;
1236
                state <= LOAD_MAC1;
1237
                retstate <= LOAD_MAC1;
1238 5 robfinch
                cyc_o <= 1'b0;
1239
                stb_o <= 1'b0;
1240
                we_o <= 1'b0;
1241
                sel_o <= 4'h0;
1242
                adr_o <= 34'd0;
1243
                dat_o <= 32'd0;
1244
                radr <= ir[39:8] + x;
1245
                isp <= isp_dec;
1246
                if (dhit) begin
1247
                        wrsel <= sel_o;
1248
                        wr <= 1'b1;
1249
                end
1250 10 robfinch
                else if (write_allocate) begin
1251
                        dmiss <= `TRUE;
1252
                        state <= WAIT_DHIT;
1253
                end
1254 5 robfinch
        end
1255 20 robfinch
 
1256 5 robfinch
JSR161:
1257
        if (ack_i) begin
1258 10 robfinch
                state <= IFETCH;
1259
                retstate <= IFETCH;
1260 5 robfinch
                cyc_o <= 1'b0;
1261
                stb_o <= 1'b0;
1262
                we_o <= 1'b0;
1263
                sel_o <= 4'h0;
1264
                pc <= {{16{ir[23]}},ir[23:8]};
1265
                isp <= isp_dec;
1266
                if (dhit) begin
1267
                        wrsel <= sel_o;
1268
                        wr <= 1'b1;
1269
                end
1270 10 robfinch
                else if (write_allocate) begin
1271
                        state <= WAIT_DHIT;
1272
                        dmiss <= `TRUE;
1273
                end
1274 5 robfinch
        end
1275
 
1276
`include "byte_irq.v"
1277
 
1278
IRQ1:
1279
        if (ack_i) begin
1280 21 robfinch
                ir <= 64'd0;            // Force instruction decoder to BRK
1281 10 robfinch
                state <= IRQ2;
1282
                retstate <= IRQ2;
1283 5 robfinch
                cyc_o <= 1'b0;
1284
                stb_o <= 1'b0;
1285
                we_o <= 1'b0;
1286
                sel_o <= 4'h0;
1287
                isp <= isp_dec;
1288
                if (dhit) begin
1289
                        wrsel <= sel_o;
1290
                        wr <= 1'b1;
1291
                end
1292 10 robfinch
                else if (write_allocate) begin
1293
                        state <= WAIT_DHIT;
1294
                        dmiss <= `TRUE;
1295
                end
1296 5 robfinch
        end
1297
IRQ2:
1298
        begin
1299
                cyc_o <= 1'b1;
1300
                stb_o <= 1'b1;
1301
                we_o <= 1'b1;
1302
                sel_o <= 4'hF;
1303
                radr <= isp_dec;
1304
                wadr <= isp_dec;
1305
                wdat <= sr;
1306
                adr_o <= {isp_dec,2'b00};
1307
                dat_o <= sr;
1308
                state <= IRQ3;
1309
        end
1310
IRQ3:
1311
        if (ack_i) begin
1312 21 robfinch
                load_what <= `PC_310;
1313
                state <= LOAD_MAC1;
1314
                retstate <= LOAD_MAC1;
1315 5 robfinch
                cyc_o <= 1'b0;
1316
                stb_o <= 1'b0;
1317
                we_o <= 1'b0;
1318
                sel_o <= 4'h0;
1319
                isp <= isp_dec;
1320
                if (dhit) begin
1321
                        wrsel <= sel_o;
1322
                        wr <= 1'b1;
1323
                end
1324 10 robfinch
                else if (write_allocate) begin
1325
                        dmiss <= `TRUE;
1326
                        state <= WAIT_DHIT;
1327
                end
1328 5 robfinch
                radr <= vect[31:2];
1329 25 robfinch
                if (hwi)
1330 5 robfinch
                        im <= 1'b1;
1331
                em <= 1'b0;                     // make sure we process in native mode; we might have been called up during emulation mode
1332
        end
1333 21 robfinch
 
1334 12 robfinch
MULDIV1:
1335
        state <= MULDIV2;
1336
MULDIV2:
1337
        if (md_done) begin
1338
                state <= IFETCH;
1339
                case(ir[23:20])
1340
                `MUL_RR:        begin res <= prod[31:0]; end
1341
                `MULS_RR:       begin res <= prod[31:0]; end
1342
                `DIV_RR:        begin res <= q; end
1343
                `DIVS_RR:       begin res <= q; end
1344
                `MOD_RR:        begin res <= r; end
1345
                `MODS_RR:       begin res <= r; end
1346
                endcase
1347
        end
1348
 
1349 21 robfinch
BUS_ERROR:
1350
        begin
1351
                radr <= isp_dec;
1352
                wadr <= isp_dec;
1353 23 robfinch
                wdat <= opc;
1354
                if (em | isOrb | isStb)
1355
                        derr_address <= adr_o[31:0];
1356
                else
1357
                        derr_address <= adr_o[33:2];
1358 21 robfinch
                cyc_o <= 1'b1;
1359
                stb_o <= 1'b1;
1360
                we_o <= 1'b1;
1361
                sel_o <= 4'hF;
1362
                adr_o <= {isp_dec,2'b00};
1363 23 robfinch
                dat_o <= opc;
1364 21 robfinch
                vect <= {vbr[31:9],9'd508,2'b00};
1365 25 robfinch
                hwi <= `TRUE;
1366 21 robfinch
                state <= IRQ1;
1367
        end
1368
INSN_BUS_ERROR:
1369
        begin
1370
                radr <= isp_dec;
1371
                wadr <= isp_dec;
1372 23 robfinch
                wdat <= opc;
1373 21 robfinch
                cyc_o <= 1'b1;
1374
                stb_o <= 1'b1;
1375
                we_o <= 1'b1;
1376
                sel_o <= 4'hF;
1377
                adr_o <= {isp_dec,2'b00};
1378 23 robfinch
                dat_o <= opc;
1379 21 robfinch
                vect <= {vbr[31:9],9'd509,2'b00};
1380 25 robfinch
                hwi <= `TRUE;
1381 21 robfinch
                state <= IRQ1;
1382
        end
1383 25 robfinch
/*
1384 23 robfinch
MVN1:
1385
        begin
1386
                radr <= x;
1387
                x <= x + 32'd1;
1388
                retstate <= MVN2;
1389
                load_what <= `WORD_312;
1390
                state <= LOAD_MAC1;
1391
        end
1392
MVN2:
1393
        begin
1394 25 robfinch
                radr <= y;
1395 23 robfinch
                wadr <= y;
1396
                wdat <= b;
1397
                y <= y + 32'd1;
1398
                acc <= acc - 32'd1;
1399
                state <= STORE1;
1400
        end
1401
MVN3:
1402
        begin
1403
                state <= IFETCH;
1404
                if (acc==32'hFFFFFFFF)
1405
                        pc <= pc + 32'd1;
1406
        end
1407
MVP1:
1408
        begin
1409
                radr <= x;
1410
                x <= x - 32'd1;
1411
                retstate <= MVP2;
1412
                load_what <= `WORD_312;
1413
                state <= LOAD_MAC1;
1414
        end
1415
MVP2:
1416
        begin
1417 25 robfinch
                radr <= y;
1418 23 robfinch
                wadr <= y;
1419
                wdat <= b;
1420
                y <= y - 32'd1;
1421
                acc <= acc - 32'd1;
1422
                state <= STORE1;
1423
        end
1424 25 robfinch
*/
1425 5 robfinch
endcase
1426
 
1427
`include "cache_controller.v"
1428
 
1429
end
1430
endmodule

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