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`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// rtf65002.v
//  - 32 bit CPU
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
`include "rtf65002_defines.v"
 
module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o, km_o);
parameter RESET1 = 6'd0;
parameter IFETCH = 6'd1;
parameter DECODE = 6'd2;
parameter STORE1 = 6'd3;
parameter STORE2 = 6'd4;
parameter CALC = 6'd5;
parameter JSR161 = 6'd6;
parameter RTS1 = 6'd7;
parameter IY3 = 6'd8;
parameter BSR1 = 6'd9;
parameter BYTE_IX5 = 6'd10;
parameter BYTE_IY5 = 6'd11;
parameter WAIT_DHIT = 6'd12;
parameter RESET2 = 6'd13;
parameter MULDIV1 = 6'd14;
parameter MULDIV2 = 6'd15;
parameter BYTE_DECODE = 6'd16;
parameter BYTE_CALC = 6'd17;
parameter BUS_ERROR = 6'd18;
parameter INSN_BUS_ERROR = 6'd19;
parameter LOAD_MAC1 = 6'd20;
parameter LOAD_MAC2 = 6'd21;
parameter LOAD_MAC3 = 6'd22;
parameter MVN3 = 6'd23;
parameter PUSHA1 = 6'd24;
parameter POPA1 = 6'd25;
parameter BYTE_IFETCH = 6'd26;
parameter LOAD_DCACHE = 6'd27;
parameter LOAD_ICACHE = 6'd28;
parameter LOAD_IBUF1 = 6'd29;
parameter LOAD_IBUF2 = 6'd30;
parameter LOAD_IBUF3 = 6'd31;
parameter ICACHE1 = 6'd32;
parameter IBUF1 = 6'd33;
parameter DCACHE1 = 6'd34;
parameter CMPS1 = 6'd35;
 
input rst_md;           // reset mode, 1=emulation mode, 0=native mode
input rst_i;
input clk_i;
input nmi_i;
input irq_i;
input [8:0] irq_vect;
output reg [1:0] bte_o;
output reg [2:0] cti_o;
output reg [5:0] bl_o;
output reg lock_o;
output reg cyc_o;
output reg stb_o;
input ack_i;
input err_i;
output reg we_o;
output reg [3:0] sel_o;
output reg [33:0] adr_o;
input [31:0] dat_i;
output reg [31:0] dat_o;
 
output km_o;
 
reg [5:0] state;
reg [5:0] retstate;
wire [63:0] insn;
reg [63:0] ibuf;
reg [31:0] bufadr;
reg [63:0] exbuf;
 
reg cf,nf,zf,vf,bf,im,df,em;
reg tf;         // trace mode flag
reg ttrig;      // trace trigger
reg em1;
reg gie;        // global interrupt enable (set when sp is loaded)
reg hwi;        // hardware interrupt indicator
reg nmoi;       // native mode on interrupt
wire [31:0] sr = {nf,vf,em,tf,23'b0,bf,df,im,zf,cf};
wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};
reg nmi1,nmi_edge;
reg wai;
reg [31:0] acc;
reg [31:0] x;
reg [31:0] y;
reg [7:0] sp;
reg [31:0] spage;        // stack page
wire [7:0] acc8 = acc[7:0];
wire [7:0] x8 = x[7:0];
wire [7:0] y8 = y[7:0];
reg [31:0] isp;          // interrupt stack pointer
wire [63:0] prod;
wire [31:0] q,r;
reg [31:0] tick;
wire [7:0] sp_dec = sp - 8'd1;
wire [7:0] sp_inc = sp + 8'd1;
wire [31:0] isp_dec = isp - 32'd1;
wire [31:0] isp_inc = isp + 32'd1;
reg [3:0] suppress_pcinc;
reg [31:0] pc;
reg [31:0] opc;
wire [3:0] pc_inc,pc_inc8;
wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc);        // for branches
wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc);        // for branches
wire [31:0] pcp8 = pc + 32'd8;                                           // cache controller needs this
reg [31:0] abs8; // 8 bit mode absolute address register
reg [31:0] vbr;          // vector table base register
wire bhit=pc==bufadr;
reg [31:0] regfile [15:0];
reg [63:0] ir;
reg pg2;
wire [8:0] ir9 = {pg2,ir[7:0]};
wire [3:0] Ra = ir[11:8];
wire [3:0] Rb = ir[15:12];
reg [31:0] rfoa;
reg [31:0] rfob;
always @(Ra or x or y or acc)
case(Ra)
4'h0:   rfoa <= 32'd0;
4'h1:   rfoa <= acc;
4'h2:   rfoa <= x;
4'h3:   rfoa <= y;
default:        rfoa <= regfile[Ra];
endcase
always @(Rb or x or y or acc)
case(Rb)
4'h0:   rfob <= 32'd0;
4'h1:   rfob <= acc;
4'h2:   rfob <= x;
4'h3:   rfob <= y;
default:        rfob <= regfile[Rb];
endcase
reg [3:0] Rt;
reg [33:0] ea;
reg first_ifetch;
reg [31:0] lfsr;
wire lfsr_fb;
xnor(lfsr_fb,lfsr[0],lfsr[1],lfsr[21],lfsr[31]);
reg [31:0] a, b;
wire signed [31:0] as = a;
wire signed [31:0] bs = b;
wire lt = as < bs;
wire eq = a==b;
wire ltu = a < b;
 
reg [7:0] b8;
wire [32:0] alu_out;
reg [32:0] res;
reg [8:0] res8;
wire resv8,resv32;
wire resc8 = res8[8];
wire resc32 = res[32];
wire resz8 = res8[7:0]==8'h00;
wire resz32 = res[31:0]==32'd0;
wire resn8 = res8[7];
wire resn32 = res[31];
 
reg [31:0] vect;
reg [31:0] ia;                   // temporary reg to hold indirect address
reg isInsnCacheLoad;
reg isDataCacheLoad;
reg isCacheReset;
wire hit0,hit1;
`ifdef SUPPORT_DCACHE
wire dhit;
`else
wire dhit = 1'b0;
`endif
reg write_allocate;
wire wr;
reg [3:0] wrsel;
reg [31:0] radr;
reg [1:0] radr2LSB;
wire [33:0] radr34 = {radr,radr2LSB};
wire [33:0] radr34p1 = radr34 + 34'd1;
reg [31:0] wadr;
reg [1:0] wadr2LSB;
reg [31:0] wdat;
wire [31:0] rdat;
reg [4:0] load_what;
reg [5:0] store_what;
reg [31:0] derr_address;
reg imiss;
reg dmiss;
reg icacheOn,dcacheOn;
`ifdef SUPPORT_DCACHE
wire unCachedData = radr[31:20]==12'hFFD || !dcacheOn;  // I/O area is uncached
`else
wire unCachedData = 1'b1;
`endif
`ifdef SUPPORT_ICACHE
wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn;              // The lowest 8kB is uncached.
`else
wire unCachedInsn = 1'b1;
`endif
`ifdef ICACHE_2WAY
reg [31:0] clfsr;
wire clfsr_fb;
xnor(clfsr_fb,clfsr[0],clfsr[1],clfsr[21],clfsr[31]);
wire [1:0] whichrd;
wire whichwr=clfsr[0];
`endif
reg km;                 // kernel mode indicator
assign km_o = km;
 
reg [31:0] history_buf [127:0];
reg [6:0] history_ndx;
reg hist_capture;
 
reg isBusErr;
reg isBrk,isMove,isSts;
reg isRTI,isRTL,isRTS;
reg isOrb,isStb;
reg isRMW;
reg isSub,isSub8;
reg isJsrIndx,isJsrInd;
reg ldMuldiv;
reg isPusha,isPopa;
 
wire isCmp = ir9==`CPX_ZPX || ir9==`CPX_ABS || ir9==`CPX_IMM32 ||
                         ir9==`CPY_ZPX || ir9==`CPY_ABS || ir9==`CPY_IMM32;
wire isRMW32 =
                         ir9==`ASL_ZPX || ir9==`ROL_ZPX || ir9==`LSR_ZPX || ir9==`ROR_ZPX || ir9==`INC_ZPX || ir9==`DEC_ZPX ||
                         ir9==`ASL_ABS || ir9==`ROL_ABS || ir9==`LSR_ABS || ir9==`ROR_ABS || ir9==`INC_ABS || ir9==`DEC_ABS ||
                         ir9==`ASL_ABSX || ir9==`ROL_ABSX || ir9==`LSR_ABSX || ir9==`ROR_ABSX || ir9==`INC_ABSX || ir9==`DEC_ABSX ||
                         ir9==`TRB_ZP || ir9==`TRB_ZPX || ir9==`TRB_ABS || ir9==`TSB_ZP || ir9==`TSB_ZPX || ir9==`TSB_ABS ||
                         ir9==`BMS_ZPX || ir9==`BMS_ABS || ir9==`BMS_ABSX ||
                         ir9==`BMC_ZPX || ir9==`BMC_ABS || ir9==`BMC_ABSX ||
                         ir9==`BMF_ZPX || ir9==`BMF_ABS || ir9==`BMF_ABSX
                         ;
wire isRMW8 =
                         ir9==`ASL_ZP || ir9==`ROL_ZP || ir9==`LSR_ZP || ir9==`ROR_ZP || ir9==`INC_ZP || ir9==`DEC_ZP ||
                         ir9==`ASL_ZPX || ir9==`ROL_ZPX || ir9==`LSR_ZPX || ir9==`ROR_ZPX || ir9==`INC_ZPX || ir9==`DEC_ZPX ||
                         ir9==`ASL_ABS || ir9==`ROL_ABS || ir9==`LSR_ABS || ir9==`ROR_ABS || ir9==`INC_ABS || ir9==`DEC_ABS ||
                         ir9==`ASL_ABSX || ir9==`ROL_ABSX || ir9==`LSR_ABSX || ir9==`ROR_ABSX || ir9==`INC_ABSX || ir9==`DEC_ABSX ||
                         ir9==`TRB_ZP || ir9==`TRB_ZPX || ir9==`TRB_ABS || ir9==`TSB_ZP || ir9==`TSB_ZPX || ir9==`TSB_ABS;
                         ;
 
// Registerable decodes
// The following decodes can be registered because they aren't needed until at least the cycle after
// the DECODE stage.
 
always @(posedge clk)
        if (state==DECODE||state==BYTE_DECODE) begin
                isSub <= ir9==`SUB_ZPX || ir9==`SUB_IX || ir9==`SUB_IY ||
                         ir9==`SUB_ABS || ir9==`SUB_ABSX || ir9==`SUB_IMM8 || ir9==`SUB_IMM16 || ir9==`SUB_IMM32;
                isSub8 <= ir9==`SBC_ZP || ir9==`SBC_ZPX || ir9==`SBC_IX || ir9==`SBC_IY || ir9==`SBC_I ||
                         ir9==`SBC_ABS || ir9==`SBC_ABSX || ir9==`SBC_ABSY || ir9==`SBC_IMM;
                isRMW <= em ? isRMW8 : isRMW32;
                isOrb <= ir9==`ORB_ZPX || ir9==`ORB_IX || ir9==`ORB_IY || ir9==`ORB_ABS || ir9==`ORB_ABSX;
                isStb <= ir9==`STB_ZPX || ir9==`STB_ABS || ir9==`STB_ABSX;
                isRTI <= ir9==`RTI;
                isRTL <= ir9==`RTL;
                isRTS <= ir9==`RTS;
                isBrk <= ir9==`BRK;
                isMove <= ir9==`MVP || ir9==`MVN;
                isSts <= ir9==`STS;
                isJsrIndx <= ir9==`JSR_INDX;
                isJsrInd <= ir9==`JSR_IND;
                ldMuldiv <= ir9==`MUL_IMM8 || ir9==`DIV_IMM8 || ir9==`MOD_IMM8 || (ir9==`RR && (
                        ir[23:20]==`MUL_RR || ir[23:20]==`MULS_RR || ir[23:20]==`DIV_RR || ir[23:20]==`DIVS_RR || ir[23:20]==`MOD_RR || ir[23:20]==`MODS_RR));
                isPusha <= ir9==`PUSHA;
                isPopa <= ir9==`POPA;
        end
        else
                ldMuldiv <= 1'b0;
 
`ifdef SUPPORT_EXEC
wire isExec = ir9==`EXEC;
wire isAtni = ir9==`ATNI;
`else
wire isExec = 1'b0;
wire isAtni = 1'b0;
`endif
wire md_done;
wire clk;
reg isIY;
 
rtf65002_pcinc upci1
(
        .opcode(ir9),
        .suppress_pcinc(suppress_pcinc),
        .inc(pc_inc)
);
 
rtf65002_pcinc8 upci2
(
        .opcode(ir[7:0]),
        .suppress_pcinc(suppress_pcinc),
        .inc(pc_inc8)
);
 
mult_div umd1
(
        .rst(rst_i),
        .clk(clk),
        .ld(ldMuldiv),
        .op(ir9),
        .fn(ir[23:20]),
        .a(a),
        .b(b),
        .p(prod),
        .q(q),
        .r(r),
        .done(md_done)
);
 
`ifdef SUPPORT_ICACHE
`ifdef ICACHE_2WAY
rtf65002_icachemem2way icm0 (
        .whichrd(whichrd),
        .whichwr(whichwr),
        .wclk(clk),
        .wr(ack_i & isInsnCacheLoad),
        .adr(adr_o),
        .dat(dat_i),
        .rclk(~clk),
        .pc(pc),
        .insn(insn)
);
 
rtf65002_itagmem2way tgm0 (
        .whichrd(whichrd),
        .whichwr(isCacheReset ? adr_o[13]: whichwr),
        .wclk(clk),
        .wr((ack_i & isInsnCacheLoad)|isCacheReset),
        .adr({adr_o[31:1],!isCacheReset}),
        .rclk(~clk),
        .pc(pc),
        .hit0(hit0),
        .hit1(hit1)
);
`else
`ifdef ICACHE_4K
rtf65002_icachemem4k icm0 (
        .wclk(clk),
        .wr(ack_i & isInsnCacheLoad),
        .adr(adr_o),
        .dat(dat_i),
        .rclk(~clk),
        .pc(pc),
        .insn(insn)
);
 
rtf65002_itagmem4k tgm0 (
        .wclk(clk),
        .wr((ack_i & isInsnCacheLoad)|isCacheReset),
        .adr({adr_o[31:1],!isCacheReset}),
        .rclk(~clk),
        .pc(pc),
        .hit0(hit0),
        .hit1(hit1)
);
`endif
`ifdef ICACHE_8K
rtf65002_icachemem8k icm0 (
        .wclk(clk),
        .wr(ack_i & isInsnCacheLoad),
        .adr(adr_o),
        .dat(dat_i),
        .rclk(~clk),
        .pc(pc),
        .insn(insn)
);
 
rtf65002_itagmem8k tgm0 (
        .wclk(clk),
        .wr((ack_i & isInsnCacheLoad)|isCacheReset),
        .adr({adr_o[31:1],!isCacheReset}),
        .rclk(~clk),
        .pc(pc),
        .hit0(hit0),
        .hit1(hit1)
);
`endif
`ifdef ICACHE_16K
rtf65002_icachemem icm0 (
        .wclk(clk),
        .wr(ack_i & isInsnCacheLoad),
        .adr(adr_o),
        .dat(dat_i),
        .rclk(~clk),
        .pc(pc),
        .insn(insn)
);
 
rtf65002_itagmem tgm0 (
        .wclk(clk),
        .wr((ack_i & isInsnCacheLoad)|isCacheReset),
        .adr({adr_o[31:1],!isCacheReset}),
        .rclk(~clk),
        .pc(pc),
        .hit0(hit0),
        .hit1(hit1)
);
`endif
`endif  // ICACHE_2WAY
 
wire ihit = (hit0 & hit1);//(pc[2:0] > 3'd1 ? hit1 : 1'b1));
`else
wire ihit = 1'b0;
`endif
 
`ifdef SUPPORT_DCACHE
assign wr = state==STORE2 && dhit && ack_i;
 
rtf65002_dcachemem dcm0 (
        .wclk(clk),
        .wr(wr | (ack_i & isDataCacheLoad)),
        .sel(sel_o),
        .wadr(adr_o[33:2]),
        .wdat(wr ? dat_o : dat_i),
        .rclk(~clk),
        .radr(radr),
        .rdat(rdat)
);
 
rtf65002_dtagmem dtm0 (
        .wclk(clk),
        .wr(wr | (ack_i & isDataCacheLoad) | isCacheReset),
        .wadr(adr_o[33:2]),
        .cr(!isCacheReset),
        .rclk(~clk),
        .radr(radr),
        .hit(dhit)
);
`endif
 
overflow uovr1 (
        .op(isSub),
        .a(a[31]),
        .b(b[31]),
        .s(res[31]),
        .v(resv32)
);
 
overflow uovr2 (
        .op(isSub8),
        .a(acc8[7]),
        .b(b8[7]),
        .s(res8[7]),
        .v(resv8)
);
 
wire [7:0] bcaio;
wire [7:0] bcao;
wire [7:0] bcsio;
wire [7:0] bcso;
wire bcaico,bcaco,bcsico,bcsco;
 
`ifdef SUPPORT_BCD
BCDAdd ubcdai1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcaio),.c(bcaico));
BCDAdd ubcda2 (.ci(cf),.a(acc8),.b(b8),.o(bcao),.c(bcaco));
BCDSub ubcdsi1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcsio),.c(bcsico));
BCDSub ubcds2 (.ci(cf),.a(acc8),.b(b8),.o(bcso),.c(bcsco));
`endif
 
reg [7:0] dati;
always @(radr2LSB or dat_i)
case(radr2LSB)
2'd0:   dati <= dat_i[7:0];
2'd1:   dati <= dat_i[15:8];
2'd2:   dati <= dat_i[23:16];
2'd3:   dati <= dat_i[31:24];
endcase
reg [7:0] rdat8;
always @(radr2LSB or rdat)
case(radr2LSB)
2'd0:   rdat8 <= rdat[7:0];
2'd1:   rdat8 <= rdat[15:8];
2'd2:   rdat8 <= rdat[23:16];
2'd3:   rdat8 <= rdat[31:24];
endcase
 
// Evaluate branches
// 
reg takb;
always @(ir9 or cf or vf or nf or zf)
case(ir9)
`BEQ:   takb <= zf;
`BNE:   takb <= !zf;
`BPL:   takb <= !nf;
`BMI:   takb <= nf;
`BCS:   takb <= cf;
`BCC:   takb <= !cf;
`BVS:   takb <= vf;
`BVC:   takb <= !vf;
`BRA:   takb <= 1'b1;
`BRL:   takb <= 1'b1;
`BHI:   takb <= cf & !zf;
`BLS:   takb <= !cf | zf;
`BGE:   takb <= (nf & vf)|(!nf & !vf);
`BLT:   takb <= (nf & !vf)|(!nf & vf);
`BGT:   takb <= (nf & vf & !zf) + (!nf & !vf & !zf);
`BLE:   takb <= zf | (nf & !vf)|(!nf & vf);
default:        takb <= 1'b0;
endcase
 
wire [31:0] iapy8                        = ia + y8;      // Don't add in abs8, already included with ia
wire [31:0] zp_address           = {abs8[31:16],8'h00,ir[15:8]};
wire [31:0] zpx_address  = {abs8[31:16],8'h00,ir[15:8]} + x8;
wire [31:0] zpy_address          = {abs8[31:16],8'h00,ir[15:8]} + y8;
wire [31:0] abs_address  = {abs8[31:16],ir[23:8]};
wire [31:0] absx_address         = {abs8[31:16],ir[23:8] + {8'h0,x8}};   // simulates 64k bank wrap-around
wire [31:0] absy_address         = {abs8[31:16],ir[23:8] + {8'h0,y8}};
wire [31:0] zpx32xy_address      = ir[23:12] + rfoa;
wire [31:0] absx32xy_address     = ir[47:16] + rfob;
wire [31:0] zpx32_address                = ir[31:20] + rfob;
wire [31:0] absx32_address               = ir[55:24] + rfob;
 
rtf65002_alu ualu1
(
        .clk(clk),
        .state(state),
        .resin(res),
        .pg2(pg2),
        .ir(ir),
        .acc(acc),
        .x(x),
        .y(y),
        .isp(isp),
        .rfoa(rfoa),
        .rfob(rfob),
        .a(a),
        .b(b),
        .b8(b8),
        .Rt(Rt),
        .icacheOn(icacheOn),
        .dcacheOn(dcacheOn),
        .write_allocate(write_allocate),
        .prod(prod),
        .tick(tick),
        .lfsr(lfsr),
        .abs8(abs8),
        .vbr(vbr),
        .nmoi(nmoi),
        .derr_address(derr_address),
        .history_buf(history_buf[history_ndx]),
        .spage(spage),
        .sp(sp),
        .df(df),
        .cf(cf),
        .res(alu_out)
);
 
 
//-----------------------------------------------------------------------------
// Clock control
// - reset or NMI reenables the clock
// - this circuit must be under the clk_i domain
//-----------------------------------------------------------------------------
//
reg cpu_clk_en;
reg clk_en;
BUFGCE u20 (.CE(cpu_clk_en), .I(clk_i), .O(clk) );
 
always @(posedge clk_i)
if (rst_i) begin
        cpu_clk_en <= 1'b1;
        nmi1 <= 1'b0;
end
else begin
        nmi1 <= nmi_i;
        if (nmi_i)
                cpu_clk_en <= 1'b1;
        else
                cpu_clk_en <= clk_en;
end
 
always @(posedge clk)
if (rst_i) begin
        bte_o <= 2'b00;
        cti_o <= 3'b000;
        bl_o <= 6'd0;
        cyc_o <= 1'b0;
        stb_o <= 1'b0;
        we_o <= 1'b0;
        sel_o <= 4'h0;
        adr_o <= 34'd0;
        dat_o <= 32'd0;
        nmi_edge <= 1'b0;
        wai <= 1'b0;
        first_ifetch <= `TRUE;
        cf <= 1'b0;
        ir <= 64'hEAEAEAEAEAEAEAEA;
        imiss <= `FALSE;
        dmiss <= `FALSE;
        dcacheOn <= 1'b0;
        icacheOn <= 1'b1;
        write_allocate <= 1'b0;
        nmoi <= 1'b1;
        state <= RESET1;
        if (rst_md) begin
                pc <= 32'h0000FFF0;             // set high-order pc to zero
                vect <= `BYTE_RST_VECT;
                em <= 1'b1;
        end
        else begin
                vect <= `RST_VECT;
                em <= 1'b0;
                pc <= 32'hFFFFFFF0;
        end
        suppress_pcinc <= 4'hF;
        exbuf <= 64'd0;
        spage <= 32'h00000100;
        bufadr <= 32'd0;
        abs8 <= 32'd0;
        clk_en <= 1'b1;
        isCacheReset <= `TRUE;
        gie <= 1'b0;
        tick <= 32'd0;
        isIY <= 1'b0;
        load_what <= `NOTHING;
        hist_capture <= `TRUE;
        history_ndx <= 6'd0;
        pg2 <= `FALSE;
        tf <= `FALSE;
        km <= `TRUE;
end
else begin
tick <= tick + 32'd1;
if (nmi_i & !nmi1)
        nmi_edge <= 1'b1;
if (nmi_i|nmi1)
        clk_en <= 1'b1;
case(state)
// Loop in this state until all the cache address tage have been flagged as
// invalid.
//
RESET1:
        begin
                adr_o <= adr_o + 32'd4;
                if (adr_o[13:4]==10'h3FF) begin
                        state <= RESET2;
                        isCacheReset <= `FALSE;
                end
        end
RESET2:
        begin
                radr <= vect[31:2];
                radr2LSB <= vect[1:0];
                load_what <= em ? `PC_70 : `PC_310;
                state <= LOAD_MAC1;
        end
 
`include "ifetch.v"
`ifdef SUPPORT_EM8
`include "byte_ifetch.v"
`include "byte_decode.v"
`include "byte_calc.v"
`endif
 
`include "load_mac.v"
`include "store.v"
 
// This state waits for a data hit before continuing. It's used after a store 
// operation when write allocation is taking place.
WAIT_DHIT:
        if (dhit)
                state <= retstate;
 
DECODE: decode_tsk();
CALC:   calc_tsk();
 
MULDIV1:        state <= MULDIV2;
MULDIV2:
        if (md_done) begin
                state <= IFETCH;
                case(ir9)
                `RR:
                        case(ir[23:20])
                        `MUL_RR:        begin res <= prod[31:0]; end
                        `MULS_RR:       begin res <= prod[31:0]; end
`ifdef SUPPORT_DIVMOD
                        `DIV_RR:        begin res <= q; end
                        `DIVS_RR:       begin res <= q; end
                        `MOD_RR:        begin res <= r; end
                        `MODS_RR:       begin res <= r; end
`endif
                        endcase
                `MUL_IMM8,`MUL_IMM16,`MUL_IMM32:        res <= prod[31:0];
`ifdef SUPPORT_DIVMOD
                `DIV_IMM8,`DIV_IMM16,`DIV_IMM32:        res <= q;
                `MOD_IMM8,`MOD_IMM16,`MOD_IMM32:        res <= r;
`endif
                endcase
        end
 
`ifdef SUPPORT_BERR
BUS_ERROR:
        begin
                pg2 <= `FALSE;
                ir <= {8{`BRK}};
                hist_capture <= `FALSE;
                radr <= isp_dec;
                wadr <= isp_dec;
                isp <= isp_dec;
                store_what <= `STW_OPC;
                if (em | isOrb | isStb)
                        derr_address <= adr_o[31:0];
                else
                        derr_address <= adr_o[33:2];
                vect <= {vbr[31:9],9'd508,2'b00};
                hwi <= `TRUE;
                isBusErr <= `TRUE;
                state <= STORE1;
        end
INSN_BUS_ERROR:
        begin
                pg2 <= `FALSE;
                ir <= {8{`BRK}};
                hist_capture <= `FALSE;
                radr <= isp_dec;
                wadr <= isp_dec;
                isp <= isp_dec;
                store_what <= `STW_OPC;
                derr_address <= 34'd0;
                vect <= {vbr[31:9],9'd509,2'b00};
                hwi <= `TRUE;
                isBusErr <= `TRUE;
                state <= STORE1;
        end
`endif
 
`include "rtf65002_string.v"
`include "cache_controller.v"
 
endcase
end
`include "decode.v"
`include "calc.v"
`include "load_tsk.v"
 
endmodule

Line No.	Rev	Author	Line
1	10	robfinch	`timescale 1ns / 1ps
2			`// ============================================================================`
3			`// __`
4			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
5			`// \ __ / All rights reserved.`
6			`// \/_// robfinch<remove>@opencores.org`
7			`// \|\|`
8			`//`
9			`// rtf65002.v`
10			`// - 32 bit CPU`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`// ============================================================================`
26			`//`
27	30	robfinch	`include "rtf65002_defines.v"
28	5	robfinch
29	32	robfinch	`module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o, km_o);`
30	30	robfinch	`parameter RESET1 = 6'd0;`
31			`parameter IFETCH = 6'd1;`
32			`parameter DECODE = 6'd2;`
33			`parameter STORE1 = 6'd3;`
34			`parameter STORE2 = 6'd4;`
35	32	robfinch	`parameter CALC = 6'd5;`
36			`parameter JSR161 = 6'd6;`
37			`parameter RTS1 = 6'd7;`
38			`parameter IY3 = 6'd8;`
39			`parameter BSR1 = 6'd9;`
40			`parameter BYTE_IX5 = 6'd10;`
41			`parameter BYTE_IY5 = 6'd11;`
42			`parameter WAIT_DHIT = 6'd12;`
43			`parameter RESET2 = 6'd13;`
44			`parameter MULDIV1 = 6'd14;`
45			`parameter MULDIV2 = 6'd15;`
46			`parameter BYTE_DECODE = 6'd16;`
47			`parameter BYTE_CALC = 6'd17;`
48			`parameter BUS_ERROR = 6'd18;`
49			`parameter INSN_BUS_ERROR = 6'd19;`
50			`parameter LOAD_MAC1 = 6'd20;`
51			`parameter LOAD_MAC2 = 6'd21;`
52			`parameter LOAD_MAC3 = 6'd22;`
53			`parameter MVN3 = 6'd23;`
54			`parameter PUSHA1 = 6'd24;`
55			`parameter POPA1 = 6'd25;`
56			`parameter BYTE_IFETCH = 6'd26;`
57			`parameter LOAD_DCACHE = 6'd27;`
58			`parameter LOAD_ICACHE = 6'd28;`
59			`parameter LOAD_IBUF1 = 6'd29;`
60			`parameter LOAD_IBUF2 = 6'd30;`
61			`parameter LOAD_IBUF3 = 6'd31;`
62			`parameter ICACHE1 = 6'd32;`
63			`parameter IBUF1 = 6'd33;`
64			`parameter DCACHE1 = 6'd34;`
65			`parameter CMPS1 = 6'd35;`
66	5	robfinch
67	21	robfinch	`input rst_md; // reset mode, 1=emulation mode, 0=native mode`
68	5	robfinch	`input rst_i;`
69			`input clk_i;`
70			`input nmi_i;`
71			`input irq_i;`
72	13	robfinch	`input [8:0] irq_vect;`
73	5	robfinch	`output reg [1:0] bte_o;`
74			`output reg [2:0] cti_o;`
75			`output reg [5:0] bl_o;`
76			`output reg lock_o;`
77			`output reg cyc_o;`
78			`output reg stb_o;`
79			`input ack_i;`
80	21	robfinch	`input err_i;`
81	5	robfinch	`output reg we_o;`
82			`output reg [3:0] sel_o;`
83			`output reg [33:0] adr_o;`
84			`input [31:0] dat_i;`
85			`output reg [31:0] dat_o;`
86
87	32	robfinch	`output km_o;`
88
89	30	robfinch	`reg [5:0] state;`
90			`reg [5:0] retstate;`
91	21	robfinch	`wire [63:0] insn;`
92			`reg [63:0] ibuf;`
93	5	robfinch	`reg [31:0] bufadr;`
94	25	robfinch	`reg [63:0] exbuf;`
95	5	robfinch
96			`reg cf,nf,zf,vf,bf,im,df,em;`
97	32	robfinch	`reg tf; // trace mode flag`
98			`reg ttrig; // trace trigger`
99	5	robfinch	`reg em1;`
100	32	robfinch	`reg gie; // global interrupt enable (set when sp is loaded)`
101	25	robfinch	`reg hwi; // hardware interrupt indicator`
102	5	robfinch	`reg nmoi; // native mode on interrupt`
103	32	robfinch	`wire [31:0] sr = {nf,vf,em,tf,23'b0,bf,df,im,zf,cf};`
104	5	robfinch	`wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};`
105			`reg nmi1,nmi_edge;`
106			`reg wai;`
107			`reg [31:0] acc;`
108			`reg [31:0] x;`
109			`reg [31:0] y;`
110			`reg [7:0] sp;`
111	13	robfinch	`reg [31:0] spage; // stack page`
112	5	robfinch	`wire [7:0] acc8 = acc[7:0];`
113			`wire [7:0] x8 = x[7:0];`
114			`wire [7:0] y8 = y[7:0];`
115			`reg [31:0] isp; // interrupt stack pointer`
116	12	robfinch	`wire [63:0] prod;`
117			`wire [31:0] q,r;`
118			`reg [31:0] tick;`
119	5	robfinch	`wire [7:0] sp_dec = sp - 8'd1;`
120			`wire [7:0] sp_inc = sp + 8'd1;`
121			`wire [31:0] isp_dec = isp - 32'd1;`
122			`wire [31:0] isp_inc = isp + 32'd1;`
123	25	robfinch	`reg [3:0] suppress_pcinc;`
124	5	robfinch	`reg [31:0] pc;`
125	23	robfinch	`reg [31:0] opc;`
126	32	robfinch	`wire [3:0] pc_inc,pc_inc8;`
127	30	robfinch	`wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc); // for branches`
128			`wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc); // for branches`
129			`wire [31:0] pcp8 = pc + 32'd8; // cache controller needs this`
130	13	robfinch	`reg [31:0] abs8; // 8 bit mode absolute address register`
131			`reg [31:0] vbr; // vector table base register`
132	5	robfinch	`wire bhit=pc==bufadr;`
133			`reg [31:0] regfile [15:0];`
134	21	robfinch	`reg [63:0] ir;`
135	32	robfinch	`reg pg2;`
136			`wire [8:0] ir9 = {pg2,ir[7:0]};`
137	5	robfinch	`wire [3:0] Ra = ir[11:8];`
138			`wire [3:0] Rb = ir[15:12];`
139			`reg [31:0] rfoa;`
140			`reg [31:0] rfob;`
141			`always @(Ra or x or y or acc)`
142			`case(Ra)`
143			`4'h0: rfoa <= 32'd0;`
144			`4'h1: rfoa <= acc;`
145			`4'h2: rfoa <= x;`
146			`4'h3: rfoa <= y;`
147			`default: rfoa <= regfile[Ra];`
148			`endcase`
149			`always @(Rb or x or y or acc)`
150			`case(Rb)`
151			`4'h0: rfob <= 32'd0;`
152			`4'h1: rfob <= acc;`
153			`4'h2: rfob <= x;`
154			`4'h3: rfob <= y;`
155			`default: rfob <= regfile[Rb];`
156			`endcase`
157			`reg [3:0] Rt;`
158			`reg [33:0] ea;`
159			`reg first_ifetch;`
160	12	robfinch	`reg [31:0] lfsr;`
161			`wire lfsr_fb;`
162			`xnor(lfsr_fb,lfsr[0],lfsr[1],lfsr[21],lfsr[31]);`
163	5	robfinch	`reg [31:0] a, b;`
164	32	robfinch	`wire signed [31:0] as = a;`
165			`wire signed [31:0] bs = b;`
166			`wire lt = as < bs;`
167			`wire eq = a==b;`
168			`wire ltu = a < b;`
169
170	5	robfinch	`reg [7:0] b8;`
171	32	robfinch	`wire [32:0] alu_out;`
172	5	robfinch	`reg [32:0] res;`
173			`reg [8:0] res8;`
174			`wire resv8,resv32;`
175			`wire resc8 = res8[8];`
176			`wire resc32 = res[32];`
177			`wire resz8 = res8[7:0]==8'h00;`
178			`wire resz32 = res[31:0]==32'd0;`
179			`wire resn8 = res8[7];`
180			`wire resn32 = res[31];`
181
182			`reg [31:0] vect;`
183			`reg [31:0] ia; // temporary reg to hold indirect address`
184			`reg isInsnCacheLoad;`
185			`reg isDataCacheLoad;`
186	10	robfinch	`reg isCacheReset;`
187	5	robfinch	`wire hit0,hit1;`
188	30	robfinch	`ifdef SUPPORT_DCACHE
189	5	robfinch	`wire dhit;`
190	30	robfinch	`else
191			`wire dhit = 1'b0;`
192			`endif
193	10	robfinch	`reg write_allocate;`
194	32	robfinch	`wire wr;`
195	5	robfinch	`reg [3:0] wrsel;`
196			`reg [31:0] radr;`
197			`reg [1:0] radr2LSB;`
198			`wire [33:0] radr34 = {radr,radr2LSB};`
199			`wire [33:0] radr34p1 = radr34 + 34'd1;`
200			`reg [31:0] wadr;`
201			`reg [1:0] wadr2LSB;`
202			`reg [31:0] wdat;`
203			`wire [31:0] rdat;`
204	32	robfinch	`reg [4:0] load_what;`
205			`reg [5:0] store_what;`
206	23	robfinch	`reg [31:0] derr_address;`
207	5	robfinch	`reg imiss;`
208			`reg dmiss;`
209			`reg icacheOn,dcacheOn;`
210	30	robfinch	`ifdef SUPPORT_DCACHE
211	20	robfinch	`wire unCachedData = radr[31:20]==12'hFFD \|\| !dcacheOn; // I/O area is uncached`
212	30	robfinch	`else
213			`wire unCachedData = 1'b1;`
214			`endif
215			`ifdef SUPPORT_ICACHE
216	20	robfinch	`wire unCachedInsn = pc[31:13]==19'h0 \|\| !icacheOn; // The lowest 8kB is uncached.`
217	30	robfinch	`else
218			`wire unCachedInsn = 1'b1;`
219			`endif
220	32	robfinch	`ifdef ICACHE_2WAY
221			`reg [31:0] clfsr;`
222			`wire clfsr_fb;`
223			`xnor(clfsr_fb,clfsr[0],clfsr[1],clfsr[21],clfsr[31]);`
224			`wire [1:0] whichrd;`
225			`wire whichwr=clfsr[0];`
226			`endif
227			`reg km; // kernel mode indicator`
228			`assign km_o = km;`
229	5	robfinch
230	32	robfinch	`reg [31:0] history_buf [127:0];`
231			`reg [6:0] history_ndx;`
232	30	robfinch	`reg hist_capture;`
233
234	32	robfinch	`reg isBusErr;`
235	30	robfinch	`reg isBrk,isMove,isSts;`
236			`reg isRTI,isRTL,isRTS;`
237			`reg isOrb,isStb;`
238			`reg isRMW;`
239			`reg isSub,isSub8;`
240	32	robfinch	`reg isJsrIndx,isJsrInd;`
241			`reg ldMuldiv;`
242			`reg isPusha,isPopa;`
243	30	robfinch
244	32	robfinch	wire isCmp = ir9==`CPX_ZPX \|\| ir9==`CPX_ABS \|\| ir9==`CPX_IMM32 \|\|
245			ir9==`CPY_ZPX \|\| ir9==`CPY_ABS \|\| ir9==`CPY_IMM32;
246	5	robfinch	`wire isRMW32 =`
247	32	robfinch	ir9==`ASL_ZPX \|\| ir9==`ROL_ZPX \|\| ir9==`LSR_ZPX \|\| ir9==`ROR_ZPX \|\| ir9==`INC_ZPX \|\| ir9==`DEC_ZPX \|\|
248			ir9==`ASL_ABS \|\| ir9==`ROL_ABS \|\| ir9==`LSR_ABS \|\| ir9==`ROR_ABS \|\| ir9==`INC_ABS \|\| ir9==`DEC_ABS \|\|
249			ir9==`ASL_ABSX \|\| ir9==`ROL_ABSX \|\| ir9==`LSR_ABSX \|\| ir9==`ROR_ABSX \|\| ir9==`INC_ABSX \|\| ir9==`DEC_ABSX \|\|
250			ir9==`TRB_ZP \|\| ir9==`TRB_ZPX \|\| ir9==`TRB_ABS \|\| ir9==`TSB_ZP \|\| ir9==`TSB_ZPX \|\| ir9==`TSB_ABS \|\|
251			ir9==`BMS_ZPX \|\| ir9==`BMS_ABS \|\| ir9==`BMS_ABSX \|\|
252			ir9==`BMC_ZPX \|\| ir9==`BMC_ABS \|\| ir9==`BMC_ABSX \|\|
253			ir9==`BMF_ZPX \|\| ir9==`BMF_ABS \|\| ir9==`BMF_ABSX
254	5	robfinch	`;`
255			`wire isRMW8 =`
256	32	robfinch	ir9==`ASL_ZP \|\| ir9==`ROL_ZP \|\| ir9==`LSR_ZP \|\| ir9==`ROR_ZP \|\| ir9==`INC_ZP \|\| ir9==`DEC_ZP \|\|
257			ir9==`ASL_ZPX \|\| ir9==`ROL_ZPX \|\| ir9==`LSR_ZPX \|\| ir9==`ROR_ZPX \|\| ir9==`INC_ZPX \|\| ir9==`DEC_ZPX \|\|
258			ir9==`ASL_ABS \|\| ir9==`ROL_ABS \|\| ir9==`LSR_ABS \|\| ir9==`ROR_ABS \|\| ir9==`INC_ABS \|\| ir9==`DEC_ABS \|\|
259			ir9==`ASL_ABSX \|\| ir9==`ROL_ABSX \|\| ir9==`LSR_ABSX \|\| ir9==`ROR_ABSX \|\| ir9==`INC_ABSX \|\| ir9==`DEC_ABSX \|\|
260			ir9==`TRB_ZP \|\| ir9==`TRB_ZPX \|\| ir9==`TRB_ABS \|\| ir9==`TSB_ZP \|\| ir9==`TSB_ZPX \|\| ir9==`TSB_ABS;
261	5	robfinch	`;`
262	30	robfinch
263			`// Registerable decodes`
264			`// The following decodes can be registered because they aren't needed until at least the cycle after`
265			`// the DECODE stage.`
266
267			`always @(posedge clk)`
268	32	robfinch	`if (state==DECODE\|\|state==BYTE_DECODE) begin`
269			isSub <= ir9==`SUB_ZPX \|\| ir9==`SUB_IX \|\| ir9==`SUB_IY \|\|
270			ir9==`SUB_ABS \|\| ir9==`SUB_ABSX \|\| ir9==`SUB_IMM8 \|\| ir9==`SUB_IMM16 \|\| ir9==`SUB_IMM32;
271			isSub8 <= ir9==`SBC_ZP \|\| ir9==`SBC_ZPX \|\| ir9==`SBC_IX \|\| ir9==`SBC_IY \|\| ir9==`SBC_I \|\|
272			ir9==`SBC_ABS \|\| ir9==`SBC_ABSX \|\| ir9==`SBC_ABSY \|\| ir9==`SBC_IMM;
273	30	robfinch	`isRMW <= em ? isRMW8 : isRMW32;`
274	32	robfinch	isOrb <= ir9==`ORB_ZPX \|\| ir9==`ORB_IX \|\| ir9==`ORB_IY \|\| ir9==`ORB_ABS \|\| ir9==`ORB_ABSX;
275			isStb <= ir9==`STB_ZPX \|\| ir9==`STB_ABS \|\| ir9==`STB_ABSX;
276			isRTI <= ir9==`RTI;
277			isRTL <= ir9==`RTL;
278			isRTS <= ir9==`RTS;
279			isBrk <= ir9==`BRK;
280			isMove <= ir9==`MVP \|\| ir9==`MVN;
281			isSts <= ir9==`STS;
282			isJsrIndx <= ir9==`JSR_INDX;
283			isJsrInd <= ir9==`JSR_IND;
284			ldMuldiv <= ir9==`MUL_IMM8 \|\| ir9==`DIV_IMM8 \|\| ir9==`MOD_IMM8 \|\| (ir9==`RR && (
285			ir[23:20]==`MUL_RR \|\| ir[23:20]==`MULS_RR \|\| ir[23:20]==`DIV_RR \|\| ir[23:20]==`DIVS_RR \|\| ir[23:20]==`MOD_RR \|\| ir[23:20]==`MODS_RR));
286			isPusha <= ir9==`PUSHA;
287			isPopa <= ir9==`POPA;
288	30	robfinch	`end`
289	32	robfinch	`else`
290			`ldMuldiv <= 1'b0;`
291	30	robfinch
292			`ifdef SUPPORT_EXEC
293	32	robfinch	wire isExec = ir9==`EXEC;
294			wire isAtni = ir9==`ATNI;
295	30	robfinch	`else
296			`wire isExec = 1'b0;`
297			`wire isAtni = 1'b0;`
298			`endif
299	12	robfinch	`wire md_done;`
300			`wire clk;`
301	21	robfinch	`reg isIY;`
302	12	robfinch
303	30	robfinch	`rtf65002_pcinc upci1`
304			`(`
305	32	robfinch	`.opcode(ir9),`
306	30	robfinch	`.suppress_pcinc(suppress_pcinc),`
307			`.inc(pc_inc)`
308			`);`
309
310	32	robfinch	`rtf65002_pcinc8 upci2`
311			`(`
312			`.opcode(ir[7:0]),`
313			`.suppress_pcinc(suppress_pcinc),`
314			`.inc(pc_inc8)`
315			`);`
316
317	12	robfinch	`mult_div umd1`
318			`(`
319	30	robfinch	`.rst(rst_i),`
320	12	robfinch	`.clk(clk),`
321	32	robfinch	`.ld(ldMuldiv),`
322			`.op(ir9),`
323			`.fn(ir[23:20]),`
324			`.a(a),`
325			`.b(b),`
326	12	robfinch	`.p(prod),`
327			`.q(q),`
328			`.r(r),`
329			`.done(md_done)`
330			`);`
331	30	robfinch
332	32	robfinch	`ifdef SUPPORT_ICACHE
333			`ifdef ICACHE_2WAY
334			`rtf65002_icachemem2way icm0 (`
335			`.whichrd(whichrd),`
336			`.whichwr(whichwr),`
337			`.wclk(clk),`
338			`.wr(ack_i & isInsnCacheLoad),`
339			`.adr(adr_o),`
340			`.dat(dat_i),`
341			`.rclk(~clk),`
342			`.pc(pc),`
343			`.insn(insn)`
344			`);`
345
346			`rtf65002_itagmem2way tgm0 (`
347			`.whichrd(whichrd),`
348			`.whichwr(isCacheReset ? adr_o[13]: whichwr),`
349			`.wclk(clk),`
350			`.wr((ack_i & isInsnCacheLoad)\|isCacheReset),`
351			`.adr({adr_o[31:1],!isCacheReset}),`
352			`.rclk(~clk),`
353			`.pc(pc),`
354			`.hit0(hit0),`
355			`.hit1(hit1)`
356			`);`
357			`else
358			`ifdef ICACHE_4K
359			`rtf65002_icachemem4k icm0 (`
360			`.wclk(clk),`
361			`.wr(ack_i & isInsnCacheLoad),`
362			`.adr(adr_o),`
363			`.dat(dat_i),`
364			`.rclk(~clk),`
365			`.pc(pc),`
366			`.insn(insn)`
367			`);`
368
369			`rtf65002_itagmem4k tgm0 (`
370			`.wclk(clk),`
371			`.wr((ack_i & isInsnCacheLoad)\|isCacheReset),`
372			`.adr({adr_o[31:1],!isCacheReset}),`
373			`.rclk(~clk),`
374			`.pc(pc),`
375			`.hit0(hit0),`
376			`.hit1(hit1)`
377			`);`
378			`endif
379			`ifdef ICACHE_8K
380			`rtf65002_icachemem8k icm0 (`
381			`.wclk(clk),`
382			`.wr(ack_i & isInsnCacheLoad),`
383			`.adr(adr_o),`
384			`.dat(dat_i),`
385			`.rclk(~clk),`
386			`.pc(pc),`
387			`.insn(insn)`
388			`);`
389
390			`rtf65002_itagmem8k tgm0 (`
391			`.wclk(clk),`
392			`.wr((ack_i & isInsnCacheLoad)\|isCacheReset),`
393			`.adr({adr_o[31:1],!isCacheReset}),`
394			`.rclk(~clk),`
395			`.pc(pc),`
396			`.hit0(hit0),`
397			`.hit1(hit1)`
398			`);`
399			`endif
400			`ifdef ICACHE_16K
401	30	robfinch	`rtf65002_icachemem icm0 (`
402	12	robfinch	`.wclk(clk),`
403	5	robfinch	`.wr(ack_i & isInsnCacheLoad),`
404			`.adr(adr_o),`
405			`.dat(dat_i),`
406	30	robfinch	`.rclk(~clk),`
407	5	robfinch	`.pc(pc),`
408			`.insn(insn)`
409			`);`
410
411	30	robfinch	`rtf65002_itagmem tgm0 (`
412	12	robfinch	`.wclk(clk),`
413	10	robfinch	`.wr((ack_i & isInsnCacheLoad)\|isCacheReset),`
414			`.adr({adr_o[31:1],!isCacheReset}),`
415	30	robfinch	`.rclk(~clk),`
416	5	robfinch	`.pc(pc),`
417			`.hit0(hit0),`
418			`.hit1(hit1)`
419			`);`
420	32	robfinch	`endif
421			`endif // ICACHE_2WAY
422	5	robfinch
423			`wire ihit = (hit0 & hit1);//(pc[2:0] > 3'd1 ? hit1 : 1'b1));`
424	30	robfinch	`else
425			`wire ihit = 1'b0;`
426			`endif
427	5	robfinch
428	30	robfinch	`ifdef SUPPORT_DCACHE
429	32	robfinch	`assign wr = state==STORE2 && dhit && ack_i;`
430
431	30	robfinch	`rtf65002_dcachemem dcm0 (`
432	12	robfinch	`.wclk(clk),`
433	5	robfinch	`.wr(wr \| (ack_i & isDataCacheLoad)),`
434	32	robfinch	`.sel(sel_o),`
435			`.wadr(adr_o[33:2]),`
436			`.wdat(wr ? dat_o : dat_i),`
437	30	robfinch	`.rclk(~clk),`
438	5	robfinch	`.radr(radr),`
439			`.rdat(rdat)`
440			`);`
441
442	30	robfinch	`rtf65002_dtagmem dtm0 (`
443	12	robfinch	`.wclk(clk),`
444	32	robfinch	`.wr(wr \| (ack_i & isDataCacheLoad) \| isCacheReset),`
445			`.wadr(adr_o[33:2]),`
446			`.cr(!isCacheReset),`
447	30	robfinch	`.rclk(~clk),`
448	5	robfinch	`.radr(radr),`
449			`.hit(dhit)`
450			`);`
451	30	robfinch	`endif
452	5	robfinch
453			`overflow uovr1 (`
454			`.op(isSub),`
455			`.a(a[31]),`
456			`.b(b[31]),`
457			`.s(res[31]),`
458			`.v(resv32)`
459			`);`
460
461			`overflow uovr2 (`
462			`.op(isSub8),`
463			`.a(acc8[7]),`
464			`.b(b8[7]),`
465			`.s(res8[7]),`
466			`.v(resv8)`
467			`);`
468
469			`wire [7:0] bcaio;`
470			`wire [7:0] bcao;`
471			`wire [7:0] bcsio;`
472			`wire [7:0] bcso;`
473			`wire bcaico,bcaco,bcsico,bcsco;`
474
475	30	robfinch	`ifdef SUPPORT_BCD
476	5	robfinch	`BCDAdd ubcdai1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcaio),.c(bcaico));`
477			`BCDAdd ubcda2 (.ci(cf),.a(acc8),.b(b8),.o(bcao),.c(bcaco));`
478			`BCDSub ubcdsi1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcsio),.c(bcsico));`
479			`BCDSub ubcds2 (.ci(cf),.a(acc8),.b(b8),.o(bcso),.c(bcsco));`
480	30	robfinch	`endif
481	5	robfinch
482			`reg [7:0] dati;`
483			`always @(radr2LSB or dat_i)`
484			`case(radr2LSB)`
485			`2'd0: dati <= dat_i[7:0];`
486			`2'd1: dati <= dat_i[15:8];`
487			`2'd2: dati <= dat_i[23:16];`
488			`2'd3: dati <= dat_i[31:24];`
489			`endcase`
490			`reg [7:0] rdat8;`
491			`always @(radr2LSB or rdat)`
492			`case(radr2LSB)`
493			`2'd0: rdat8 <= rdat[7:0];`
494			`2'd1: rdat8 <= rdat[15:8];`
495			`2'd2: rdat8 <= rdat[23:16];`
496			`2'd3: rdat8 <= rdat[31:24];`
497			`endcase`
498
499	32	robfinch	`// Evaluate branches`
500			`//`

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