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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rti.v] - Blame information for rev 32

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
RTI1:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= RTI2;
        end
        else if (dhit) begin
                cf <= rdat[0];
                zf <= rdat[1];
                im <= rdat[2];
                df <= rdat[3];
                bf <= rdat[4];
                em1 <= rdat[29];
                vf <= rdat[30];
                nf <= rdat[31];
                isp <= isp_inc;
                radr <= isp_inc;
                state <= RTI3;
        end
        else
                dmiss <= `TRUE;
RTI2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                cf <= dat_i[0];
                zf <= dat_i[1];
                im <= dat_i[2];
                df <= dat_i[3];
                bf <= dat_i[4];
                em1 <= dat_i[29];
                vf <= dat_i[30];
                nf <= dat_i[31];
                isp <= isp_inc;
                radr <= isp_inc;
                state <= RTI3;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
RTI3:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= RTI4;
        end
        else if (dhit) begin
                isp <= isp_inc;
                em <= em1;
                pc <= rdat;
                state <= IFETCH;
        end
        else
                dmiss <= `TRUE;
RTI4:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                isp <= isp_inc;
                em <= em1;
                pc <= dat_i;
                state <= IFETCH;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`RTI1:`
24			`if (unCachedData) begin`
25			`cyc_o <= 1'b1;`
26			`stb_o <= 1'b1;`
27			`sel_o <= 4'hF;`
28			`adr_o <= {radr,2'b00};`
29			`state <= RTI2;`
30			`end`
31			`else if (dhit) begin`
32			`cf <= rdat[0];`
33			`zf <= rdat[1];`
34			`im <= rdat[2];`
35			`df <= rdat[3];`
36			`bf <= rdat[4];`
37			`em1 <= rdat[29];`
38			`vf <= rdat[30];`
39			`nf <= rdat[31];`
40			`isp <= isp_inc;`
41			`radr <= isp_inc;`
42			`state <= RTI3;`
43			`end`
44			`else`
45			dmiss <= `TRUE;
46			`RTI2:`
47			`if (ack_i) begin`
48			`cyc_o <= 1'b0;`
49			`stb_o <= 1'b0;`
50			`sel_o <= 4'h0;`
51			`cf <= dat_i[0];`
52			`zf <= dat_i[1];`
53			`im <= dat_i[2];`
54			`df <= dat_i[3];`
55			`bf <= dat_i[4];`
56			`em1 <= dat_i[29];`
57			`vf <= dat_i[30];`
58			`nf <= dat_i[31];`
59			`isp <= isp_inc;`
60			`radr <= isp_inc;`
61			`state <= RTI3;`
62			`end`
63	21	robfinch	`else if (err_i) begin`
64			`lock_o <= 1'b0;`
65			`cyc_o <= 1'b0;`
66			`stb_o <= 1'b0;`
67			`we_o <= 1'b0;`
68			`sel_o <= 4'h0;`
69			`adr_o <= 34'h0;`
70			`dat_o <= 32'h0;`
71			`state <= BUS_ERROR;`
72			`end`
73	5	robfinch	`RTI3:`
74			`if (unCachedData) begin`
75			`cyc_o <= 1'b1;`
76			`stb_o <= 1'b1;`
77			`sel_o <= 4'hF;`
78			`adr_o <= {radr,2'b00};`
79			`state <= RTI4;`
80			`end`
81			`else if (dhit) begin`
82			`isp <= isp_inc;`
83			`em <= em1;`
84			`pc <= rdat;`
85			`state <= IFETCH;`
86			`end`
87			`else`
88			dmiss <= `TRUE;
89			`RTI4:`
90			`if (ack_i) begin`
91			`cyc_o <= 1'b0;`
92			`stb_o <= 1'b0;`
93			`sel_o <= 4'h0;`
94			`adr_o <= 34'h0;`
95			`isp <= isp_inc;`
96			`em <= em1;`
97			`pc <= dat_i;`
98			`state <= IFETCH;`
99			`end`
100	21	robfinch	`else if (err_i) begin`
101			`lock_o <= 1'b0;`
102			`cyc_o <= 1'b0;`
103			`stb_o <= 1'b0;`
104			`we_o <= 1'b0;`
105			`sel_o <= 4'h0;`
106			`adr_o <= 34'h0;`
107			`dat_o <= 32'h0;`
108			`state <= BUS_ERROR;`
109			`end`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rti.v] - Blame information for rev 32