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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rts.v] - Blame information for rev 5

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RTS1:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                adr_o <= {radr,2'b00};
                state <= RTS2;
        end
        else if (dhit) begin
                isp <= isp_inc;
                pc <= rdat;
                state <= IFETCH;
        end
        else
                dmiss <= `TRUE;
RTS2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                isp <= isp_inc;
                pc <= dat_i;
                state <= IFETCH;
        end

Line No.	Rev	Author	Line
1	5	robfinch	`RTS1:`
2			`if (unCachedData) begin`
3			`cyc_o <= 1'b1;`
4			`stb_o <= 1'b1;`
5			`sel_o <= 4'hF;`
6			`adr_o <= {radr,2'b00};`
7			`state <= RTS2;`
8			`end`
9			`else if (dhit) begin`
10			`isp <= isp_inc;`
11			`pc <= rdat;`
12			`state <= IFETCH;`
13			`end`
14			`else`
15			dmiss <= `TRUE;
16			`RTS2:`
17			`if (ack_i) begin`
18			`cyc_o <= 1'b0;`
19			`stb_o <= 1'b0;`
20			`sel_o <= 4'h0;`
21			`adr_o <= 34'h0;`
22			`isp <= isp_inc;`
23			`pc <= dat_i;`
24			`state <= IFETCH;`
25			`end`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rts.v] - Blame information for rev 5