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// ============================================================================
//        __
//   \\__/ o\    (C) 2013,2014  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                            
// Memory store states
// The store states work for 8, 16 or 32 bit mode              
// ============================================================================
//
// Stores always write through to memory, then optionally update the cache if
// there was a write hit.
STORE1:
        begin
                case(store_what)
                `STW_ACC:       wb_write(0,acc);
                `STW_X:         wb_write(0,x);
                `STW_Y:         wb_write(0,y);
                `STW_PC:        wb_write(0,pc);
                `STW_PC2:       wb_write(0,pc + 32'd2);
                `STW_PCHWI:     wb_write(0,pc+{30'b0,~hwi,1'b0});
                `STW_OPC:       wb_write(0,opc);
                `STW_SR:        wb_write(0,sr);
                `STW_RFA:       wb_write(0,rfoa);
                `STW_RFA8:      wb_write(1,{4{rfoa[7:0]}});
                `STW_A:         wb_write(0,a);
                `STW_B:         wb_write(0,b);
                `STW_CALC:      wb_write(0,res[31:0]);
`ifdef SUPPORT_EM8
                `STW_ACC8:      wb_write(1,{4{acc8}});
                `STW_X8:        wb_write(1,{4{x8}});
                `STW_Y8:        wb_write(1,{4{y8}});
                `STW_Z8:        wb_write(1,{4{8'h00}});
                `STW_PC3124:    wb_write(1,{4{pc[31:24]}});
                `STW_PC2316:    wb_write(1,{4{pc[23:16]}});
                `STW_PC158:             wb_write(1,{4{pc[15:8]}});
                `STW_PC70:              wb_write(1,{4{pc[7:0]}});
                `STW_SR70:              wb_write(1,{4{sr8}});
                `STW_DEF8:              wb_write(1,{4{wdat[7:0]}});
`endif
`ifdef SUPPORT_816
                `STW_DEF70:             begin wb_write(1,{4{wdat[7:0]}}); lock_o <= 1'b1; end
                `STW_DEF158:    wb_write(1,{4{wdat[15:8]}});
                `STW_ACC70:             begin wb_write(1,{4{acc[7:0]}}); lock_o <= 1'b1; end
                `STW_ACC158:    wb_write(1,{4{acc[15:8]}});
                `STW_X70:               begin wb_write(1,{4{x[7:0]}}); lock_o <= 1'b1; end
                `STW_X158:              wb_write(1,{4{x[15:8]}});
                `STW_Y70:               begin wb_write(1,{4{y[7:0]}}); lock_o <= 1'b1; end
                `STW_Y158:              wb_write(1,{4{y[15:8]}});
                `STW_Z70:               begin wb_write(1,{4{8'h00}}); lock_o <= 1'b1; end
                `STW_Z158:              wb_write(1,{4{8'h00}});
                `STW_DBR:               wb_write(1,{4{dbr}});
                `STW_DPR158:    begin wb_write(1,{4{dpr[15:8]}}); lock_o <= 1'b1; end
                `STW_DPR70:             wb_write(1,{4{dpr[7:0]}});
                `STW_TMP158:    begin wb_write(1,{4{tmp16[15:8]}}); lock_o <= 1'b1; end
                `STW_TMP70:             wb_write(1,{4{tmp16[7:0]}});
                `STW_IA158:             begin wb_write(1,{4{ia[15:8]}}); lock_o <= 1'b1; end
                `STW_IA70:              wb_write(1,{4{ia[7:0]}});
`endif
                default:        wb_write(0,wdat);
                endcase
`ifdef SUPPORT_DCACHE
                radr <= wadr;           // Do a cache read to test the hit
`endif
                if (ir9==`PUSH)
                        Rt <= 4'h0;
                state <= STORE2;
        end
 
// Terminal state for stores. Update the data cache if there was a cache hit.
// Clear any previously set lock status
STORE2:
        // On a retry operation, restore the stack pointer which may have been
        // modified, then go back to the decode state to pick up original 
        // addresses and data. This doesn't work for block move/store
        if (rty_i) begin
                wb_nack();
                isp <= oisp;
                state <= DECODE;
        end
        else if (ack_i) begin
//              wdat <= dat_o;
                if (!em && (isMove|isSts)) begin
                        state <= MVN3;
                        retstate <= MVN3;
                end
                else begin
                        if (em) begin
                                if (isMove) begin
                                        state <= MVN816;
                                        retstate <= MVN816;
                                end
                                else begin
                                        state <= BYTE_IFETCH;
                                        retstate <= BYTE_IFETCH;
                                end
                        end
                        else begin
                                state <= IFETCH;
                                retstate <= IFETCH;
                        end
                end
                lock_o <= 1'b0;
                wb_nack();
                case(store_what)
                `STW_PC,`STW_PC2,`STW_PCHWI,`STW_OPC:
                        if (isBrk|isBusErr) begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_SR;
                                state <= STORE1;
                                retstate <= STORE1;
                        end
                `STW_SR:
                        if (isBrk|isBusErr) begin
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                retstate <= LOAD_MAC1;
                                radr <= vect[33:2];
                                ttrig <= 1'b0;
                                tf <= 1'b0;                     // turn off trace mode
                                im <= 1'b1;
                                em <= 1'b0;                     // make sure we process in native mode; we might have been called up during emulation mode
                        end
                `STW_RFA:
                        if (isPusha) begin
                                if (ir[11:8]==4'hF) begin
                                        state <= IFETCH;
                                        retstate <= IFETCH;
                                end
                                else begin
                                        state <= STORE1;
                                        retstate <= STORE1;
                                        radr <= isp_dec;
                                        wadr <= isp_dec;
                                        isp <= isp_dec;
                                end
                                ir[11:8] <= ir[11:8] + 4'd1;
                        end
`ifdef SUPPORT_816
                `STW_DEF70:
                        begin
                                lock_o <= 1'b1;
                                wadr2LSB <= wadr2LSB + 2'b01;
                                if (wadr2LSB==2'b11)
                                        wadr <= wadr + 32'd1;
                                store_what <= `STW_DEF158;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
                `STW_ACC70:
                        begin
                                lock_o <= 1'b1;
                                wadr2LSB <= wadr2LSB + 2'b01;
                                if (wadr2LSB==2'b11)
                                        wadr <= wadr + 32'd1;
                                store_what <= `STW_ACC158;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
                `STW_X70:
                        begin
                                lock_o <= 1'b1;
                                wadr2LSB <= wadr2LSB + 2'b01;
                                if (wadr2LSB==2'b11)
                                        wadr <= wadr + 32'd1;
                                store_what <= `STW_X158;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
                `STW_Y70:
                        begin
                                lock_o <= 1'b1;
                                wadr2LSB <= wadr2LSB + 2'b01;
                                if (wadr2LSB==2'b11)
                                        wadr <= wadr + 32'd1;
                                store_what <= `STW_Y158;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
                `STW_Z70:
                        begin
                                lock_o <= 1'b1;
                                wadr2LSB <= wadr2LSB + 2'b01;
                                if (wadr2LSB==2'b11)
                                        wadr <= wadr + 32'd1;
                                store_what <= `STW_Z158;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
                `STW_DPR158:
                        begin
                                set_sp();
                                store_what <= `STW_DPR70;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
                `STW_TMP158:
                        begin
                                set_sp();
                                store_what <= `STW_TMP70;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
                `STW_IA158:
                        begin
                                set_sp();
                                store_what <= `STW_IA70;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
`endif
`ifdef SUPPORT_EM8
                `STW_PC3124:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                store_what <= `STW_PC2316;
                                sp <= sp_dec;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
                `STW_PC2316:
                        begin
                                if (ir9 != `PHK) begin
                                        set_sp();
                                        store_what <= `STW_PC158;
                                        retstate <= STORE1;
                                        state <= STORE1;
                                end
                        end
                `STW_PC158:
                        begin
                                set_sp();
                                store_what <= `STW_PC70;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
                `STW_PC70:
                        begin
                                case({1'b0,ir[7:0]})
                                `BRK,`COP:
                                                begin
                                                set_sp();
                                                store_what <= `STW_SR70;
                                                retstate <= STORE1;
                                                state <= STORE1;
                                                end
                                `JSR:   begin
                                                pc[15:0] <= ir[23:8];
                                                end
                                `JSL:   begin
                                                pc[23:0] <= ir[31:8];
                                                end
                                `JSR_INDX:
                                                begin
                                                state <= LOAD_MAC1;
                                                retstate <= LOAD_MAC1;
                                                load_what <= `PC_70;
                                                radr <= absx_address[31:2];
                                                radr2LSB <= absx_address[1:0];
                                                end
                                endcase
                        end
                `STW_SR70:
                        begin
                                if (ir[7:0]==`BRK) begin
                                        load_what <= `PC_70;
                                        state <= LOAD_MAC1;
                                        retstate <= LOAD_MAC1;
                                        pc[31:16] <= abs8[31:16];
                                        radr <= vect[33:2];
                                        radr2LSB <= vect[1:0];
                                        im <= hwi;
                                end
                                else if (ir[7:0]==`COP) begin
                                        load_what <= `PC_70;
                                        state <= LOAD_MAC1;
                                        retstate <= LOAD_MAC1;
                                        pc[31:16] <= abs8[31:16];
                                        radr <= vect[33:2];
                                        radr2LSB <= vect[1:0];
                                        im <= 1'b1;
                                end
                        end
`endif
                default:
                        if (isJsrIndx) begin
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                retstate <= LOAD_MAC1;
                                radr <= ir[39:8] + x;
                        end
                        else if (isJsrInd) begin
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                retstate <= LOAD_MAC1;
                                radr <= ir[39:8];
                        end
                endcase
`ifdef SUPPORT_DCACHE
                if (!dhit && write_allocate) begin
                        state <= DCACHE1;
                end
`endif
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                lock_o <= 1'b0;
                wb_nack();
                if (em | isStb)
                        derr_address <= adr_o[31:0];
                else
                        derr_address <= adr_o[33:2];
                intno <= 9'd508;
                state <= BUS_ERROR;
        end
`endif

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3	38	robfinch	`// \\__/ o\ (C) 2013,2014 Robert Finch, Stratford`
4	20	robfinch	`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// Memory store states`
22	38	robfinch	`// The store states work for 8, 16 or 32 bit mode`
23	20	robfinch	`// ============================================================================`
24			`//`
25			`// Stores always write through to memory, then optionally update the cache if`
26			`// there was a write hit.`
27			`STORE1:`
28			`begin`
29	30	robfinch	`case(store_what)`
30	35	robfinch	`STW_ACC: wb_write(0,acc);
31			`STW_X: wb_write(0,x);
32			`STW_Y: wb_write(0,y);
33			`STW_PC: wb_write(0,pc);
34			`STW_PC2: wb_write(0,pc + 32'd2);
35			`STW_PCHWI: wb_write(0,pc+{30'b0,~hwi,1'b0});
36			`STW_OPC: wb_write(0,opc);
37			`STW_SR: wb_write(0,sr);
38			`STW_RFA: wb_write(0,rfoa);
39			`STW_RFA8: wb_write(1,{4{rfoa[7:0]}});
40			`STW_A: wb_write(0,a);
41			`STW_B: wb_write(0,b);
42			`STW_CALC: wb_write(0,res[31:0]);
43	30	robfinch	`ifdef SUPPORT_EM8
44	35	robfinch	`STW_ACC8: wb_write(1,{4{acc8}});
45			`STW_X8: wb_write(1,{4{x8}});
46			`STW_Y8: wb_write(1,{4{y8}});
47			`STW_Z8: wb_write(1,{4{8'h00}});
48			`STW_PC3124: wb_write(1,{4{pc[31:24]}});
49			`STW_PC2316: wb_write(1,{4{pc[23:16]}});
50			`STW_PC158: wb_write(1,{4{pc[15:8]}});
51			`STW_PC70: wb_write(1,{4{pc[7:0]}});
52			`STW_SR70: wb_write(1,{4{sr8}});
53	38	robfinch	`STW_DEF8: wb_write(1,{4{wdat[7:0]}});
54	30	robfinch	`endif
55	38	robfinch	`ifdef SUPPORT_816
56			`STW_DEF70: begin wb_write(1,{4{wdat[7:0]}}); lock_o <= 1'b1; end
57			`STW_DEF158: wb_write(1,{4{wdat[15:8]}});
58			`STW_ACC70: begin wb_write(1,{4{acc[7:0]}}); lock_o <= 1'b1; end
59			`STW_ACC158: wb_write(1,{4{acc[15:8]}});
60			`STW_X70: begin wb_write(1,{4{x[7:0]}}); lock_o <= 1'b1; end
61			`STW_X158: wb_write(1,{4{x[15:8]}});
62			`STW_Y70: begin wb_write(1,{4{y[7:0]}}); lock_o <= 1'b1; end
63			`STW_Y158: wb_write(1,{4{y[15:8]}});
64			`STW_Z70: begin wb_write(1,{4{8'h00}}); lock_o <= 1'b1; end
65			`STW_Z158: wb_write(1,{4{8'h00}});
66			`STW_DBR: wb_write(1,{4{dbr}});
67			`STW_DPR158: begin wb_write(1,{4{dpr[15:8]}}); lock_o <= 1'b1; end
68			`STW_DPR70: wb_write(1,{4{dpr[7:0]}});
69			`STW_TMP158: begin wb_write(1,{4{tmp16[15:8]}}); lock_o <= 1'b1; end
70			`STW_TMP70: wb_write(1,{4{tmp16[7:0]}});
71			`STW_IA158: begin wb_write(1,{4{ia[15:8]}}); lock_o <= 1'b1; end
72			`STW_IA70: wb_write(1,{4{ia[7:0]}});
73			`endif
74	35	robfinch	`default: wb_write(0,wdat);`
75	30	robfinch	`endcase`
76			`ifdef SUPPORT_DCACHE
77	20	robfinch	`radr <= wadr; // Do a cache read to test the hit`
78	30	robfinch	`endif
79	36	robfinch	if (ir9==`PUSH)
80			`Rt <= 4'h0;`
81	20	robfinch	`state <= STORE2;`
82			`end`
83
84			`// Terminal state for stores. Update the data cache if there was a cache hit.`
85			`// Clear any previously set lock status`
86			`STORE2:`
87	35	robfinch	`// On a retry operation, restore the stack pointer which may have been`
88			`// modified, then go back to the decode state to pick up original`
89			`// addresses and data. This doesn't work for block move/store`
90			`if (rty_i) begin`
91			`wb_nack();`
92			`isp <= oisp;`
93			`state <= DECODE;`
94			`end`
95			`else if (ack_i) begin`
96	38	robfinch	`// wdat <= dat_o;`
97			`if (!em && (isMove\|isSts)) begin`
98	23	robfinch	`state <= MVN3;`
99	30	robfinch	`retstate <= MVN3;`
100			`end`
101			`else begin`
102	32	robfinch	`if (em) begin`
103	38	robfinch	`if (isMove) begin`
104			`state <= MVN816;`
105			`retstate <= MVN816;`
106			`end`
107			`else begin`
108			`state <= BYTE_IFETCH;`
109			`retstate <= BYTE_IFETCH;`
110			`end`
111	32	robfinch	`end`
112			`else begin`
113			`state <= IFETCH;`
114			`retstate <= IFETCH;`
115			`end`
116	30	robfinch	`end`
117	20	robfinch	`lock_o <= 1'b0;`
118	35	robfinch	`wb_nack();`
119	30	robfinch	`case(store_what)`
120	32	robfinch	`STW_PC,`STW_PC2,`STW_PCHWI,`STW_OPC:
121			`if (isBrk\|isBusErr) begin`
122	30	robfinch	`radr <= isp_dec;`
123			`wadr <= isp_dec;`
124			`isp <= isp_dec;`
125			store_what <= `STW_SR;
126			`state <= STORE1;`
127			`retstate <= STORE1;`
128			`end`
129			`STW_SR:
130	32	robfinch	`if (isBrk\|isBusErr) begin`
131	30	robfinch	load_what <= `PC_310;
132			`state <= LOAD_MAC1;`
133			`retstate <= LOAD_MAC1;`
134	35	robfinch	`radr <= vect[33:2];`
135	32	robfinch	`ttrig <= 1'b0;`
136			`tf <= 1'b0; // turn off trace mode`
137			`im <= 1'b1;`
138	30	robfinch	`em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode`
139			`end`
140	32	robfinch	`STW_RFA:
141			`if (isPusha) begin`
142			`if (ir[11:8]==4'hF) begin`
143			`state <= IFETCH;`
144			`retstate <= IFETCH;`
145			`end`
146			`else begin`
147			`state <= STORE1;`
148			`retstate <= STORE1;`
149			`radr <= isp_dec;`
150			`wadr <= isp_dec;`
151			`isp <= isp_dec;`
152			`end`
153			`ir[11:8] <= ir[11:8] + 4'd1;`
154			`end`
155	38	robfinch	`ifdef SUPPORT_816
156			`STW_DEF70:
157			`begin`
158			`lock_o <= 1'b1;`
159			`wadr2LSB <= wadr2LSB + 2'b01;`
160			`if (wadr2LSB==2'b11)`
161			`wadr <= wadr + 32'd1;`
162			store_what <= `STW_DEF158;
163			`retstate <= STORE1;`
164			`state <= STORE1;`
165			`end`
166			`STW_ACC70:
167			`begin`
168			`lock_o <= 1'b1;`
169			`wadr2LSB <= wadr2LSB + 2'b01;`
170			`if (wadr2LSB==2'b11)`
171			`wadr <= wadr + 32'd1;`
172			store_what <= `STW_ACC158;
173			`retstate <= STORE1;`
174			`state <= STORE1;`
175			`end`
176			`STW_X70:
177			`begin`
178			`lock_o <= 1'b1;`
179			`wadr2LSB <= wadr2LSB + 2'b01;`
180			`if (wadr2LSB==2'b11)`
181			`wadr <= wadr + 32'd1;`
182			store_what <= `STW_X158;
183			`retstate <= STORE1;`
184			`state <= STORE1;`
185			`end`
186			`STW_Y70:
187			`begin`
188			`lock_o <= 1'b1;`
189			`wadr2LSB <= wadr2LSB + 2'b01;`
190			`if (wadr2LSB==2'b11)`
191			`wadr <= wadr + 32'd1;`
192			store_what <= `STW_Y158;
193			`retstate <= STORE1;`
194			`state <= STORE1;`
195			`end`
196			`STW_Z70:
197			`begin`
198			`lock_o <= 1'b1;`
199			`wadr2LSB <= wadr2LSB + 2'b01;`
200			`if (wadr2LSB==2'b11)`
201			`wadr <= wadr + 32'd1;`
202			store_what <= `STW_Z158;
203			`retstate <= STORE1;`
204			`state <= STORE1;`
205			`end`
206			`STW_DPR158:
207			`begin`
208			`set_sp();`
209			store_what <= `STW_DPR70;
210			`retstate <= STORE1;`
211			`state <= STORE1;`
212			`end`
213			`STW_TMP158:
214			`begin`
215			`set_sp();`
216			store_what <= `STW_TMP70;
217			`retstate <= STORE1;`
218			`state <= STORE1;`
219			`end`
220			`STW_IA158:
221			`begin`
222			`set_sp();`
223			store_what <= `STW_IA70;
224			`retstate <= STORE1;`
225			`state <= STORE1;`
226			`end`
227			`endif
228	30	robfinch	`ifdef SUPPORT_EM8
229			`STW_PC3124:
230			`begin`
231	32	robfinch	`radr <= {spage[31:8],sp[7:2]};`
232			`wadr <= {spage[31:8],sp[7:2]};`
233			`radr2LSB <= sp[1:0];`
234			`wadr2LSB <= sp[1:0];`
235	30	robfinch	store_what <= `STW_PC2316;
236	32	robfinch	`sp <= sp_dec;`
237	35	robfinch	`retstate <= STORE1;`
238	30	robfinch	`state <= STORE1;`
239			`end`
240			`STW_PC2316:
241			`begin`
242	38	robfinch	if (ir9 != `PHK) begin
243			`set_sp();`
244			store_what <= `STW_PC158;
245			`retstate <= STORE1;`
246			`state <= STORE1;`
247			`end`
248	30	robfinch	`end`
249			`STW_PC158:
250			`begin`
251	38	robfinch	`set_sp();`
252	30	robfinch	store_what <= `STW_PC70;
253	35	robfinch	`retstate <= STORE1;`
254	30	robfinch	`state <= STORE1;`
255			`end`
256			`STW_PC70:
257			`begin`
258	32	robfinch	`case({1'b0,ir[7:0]})`
259	38	robfinch	`BRK,`COP:
260			`begin`
261			`set_sp();`
262	32	robfinch	store_what <= `STW_SR70;
263	35	robfinch	`retstate <= STORE1;`
264	32	robfinch	`state <= STORE1;`
265			`end`
266			`JSR: begin
267	35	robfinch	`pc[15:0] <= ir[23:8];`
268	32	robfinch	`end`
269			`JSL: begin
270	38	robfinch	`pc[23:0] <= ir[31:8];`
271	32	robfinch	`end`
272			`JSR_INDX:
273			`begin`
274			`state <= LOAD_MAC1;`
275			`retstate <= LOAD_MAC1;`
276			load_what <= `PC_70;
277			`radr <= absx_address[31:2];`
278			`radr2LSB <= absx_address[1:0];`
279			`end`
280			`endcase`
281			`end`
282			`STW_SR70:
283			`begin`
284	30	robfinch	if (ir[7:0]==`BRK) begin
285	32	robfinch	load_what <= `PC_70;
286			`state <= LOAD_MAC1;`
287			`retstate <= LOAD_MAC1;`
288			`pc[31:16] <= abs8[31:16];`
289	35	robfinch	`radr <= vect[33:2];`
290	32	robfinch	`radr2LSB <= vect[1:0];`
291			`im <= hwi;`
292	30	robfinch	`end`
293	38	robfinch	else if (ir[7:0]==`COP) begin
294			load_what <= `PC_70;
295			`state <= LOAD_MAC1;`
296			`retstate <= LOAD_MAC1;`
297			`pc[31:16] <= abs8[31:16];`
298			`radr <= vect[33:2];`
299			`radr2LSB <= vect[1:0];`
300			`im <= 1'b1;`
301			`end`
302	30	robfinch	`end`
303			`endif
304	32	robfinch	`default:`
305			`if (isJsrIndx) begin`
306			load_what <= `PC_310;
307			`state <= LOAD_MAC1;`
308			`retstate <= LOAD_MAC1;`
309			`radr <= ir[39:8] + x;`
310			`end`
311			`else if (isJsrInd) begin`
312			load_what <= `PC_310;
313			`state <= LOAD_MAC1;`
314			`retstate <= LOAD_MAC1;`
315			`radr <= ir[39:8];`
316			`end`
317	30	robfinch	`endcase`
318			`ifdef SUPPORT_DCACHE
319	32	robfinch	`if (!dhit && write_allocate) begin`
320			`state <= DCACHE1;`
321	20	robfinch	`end`
322	30	robfinch	`endif
323	20	robfinch	`end`
324	30	robfinch	`ifdef SUPPORT_BERR
325	21	robfinch	`else if (err_i) begin`
326			`lock_o <= 1'b0;`
327	35	robfinch	`wb_nack();`
328			`if (em \| isStb)`
329			`derr_address <= adr_o[31:0];`
330			`else`
331			`derr_address <= adr_o[33:2];`
332			`intno <= 9'd508;`
333	21	robfinch	`state <= BUS_ERROR;`
334			`end`
335	30	robfinch	`endif

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