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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [store.v] - Blame information for rev 25

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                            
// Memory store states
// The store states work for either eight bit or 32 bit mode              
// ============================================================================
//
// Stores always write through to memory, then optionally update the cache if
// there was a write hit.
STORE1:
        begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                if (em || isStb) begin
                        case(wadr2LSB)
                        2'd0:   sel_o <= 4'b0001;
                        2'd1:   sel_o <= 4'b0010;
                        2'd2:   sel_o <= 4'b0100;
                        2'd3:   sel_o <= 4'b1000;
                        endcase
                end
                else
                        sel_o <= 4'hf;
                adr_o <= {wadr,2'b00};
                dat_o <= wdat;
                radr <= wadr;           // Do a cache read to test the hit
                state <= STORE2;
        end
 
// Terminal state for stores. Update the data cache if there was a cache hit.
// Clear any previously set lock status
STORE2:
        if (ack_i) begin
                if (isMove)
                        state <= MVN3;
                else
                        state <= IFETCH;
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                if (dhit) begin
                        wrsel <= sel_o;
                        wr <= 1'b1;
                end
                else if (write_allocate) begin
                        dmiss <= `TRUE;
                        state <= WAIT_DHIT;
                        if (isMove)
                                retstate <= MVN3;
                        else
                                retstate <= IFETCH;
                end
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
 
 

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// Memory store states`
22			`// The store states work for either eight bit or 32 bit mode`
23			`// ============================================================================`
24			`//`
25			`// Stores always write through to memory, then optionally update the cache if`
26			`// there was a write hit.`
27			`STORE1:`
28			`begin`
29			`cyc_o <= 1'b1;`
30			`stb_o <= 1'b1;`
31			`we_o <= 1'b1;`
32	25	robfinch	`if (em \|\| isStb) begin`
33	20	robfinch	`case(wadr2LSB)`
34			`2'd0: sel_o <= 4'b0001;`
35			`2'd1: sel_o <= 4'b0010;`
36			`2'd2: sel_o <= 4'b0100;`
37			`2'd3: sel_o <= 4'b1000;`
38			`endcase`
39	25	robfinch	`end`
40	20	robfinch	`else`
41			`sel_o <= 4'hf;`
42			`adr_o <= {wadr,2'b00};`
43			`dat_o <= wdat;`
44			`radr <= wadr; // Do a cache read to test the hit`
45			`state <= STORE2;`
46			`end`
47
48			`// Terminal state for stores. Update the data cache if there was a cache hit.`
49			`// Clear any previously set lock status`
50			`STORE2:`
51			`if (ack_i) begin`
52	23	robfinch	`if (isMove)`
53			`state <= MVN3;`
54			`else`
55			`state <= IFETCH;`
56	20	robfinch	`lock_o <= 1'b0;`
57			`cyc_o <= 1'b0;`
58			`stb_o <= 1'b0;`
59			`we_o <= 1'b0;`
60			`sel_o <= 4'h0;`
61			`adr_o <= 34'h0;`
62			`dat_o <= 32'h0;`
63			`if (dhit) begin`
64			`wrsel <= sel_o;`
65			`wr <= 1'b1;`
66			`end`
67			`else if (write_allocate) begin`
68			dmiss <= `TRUE;
69			`state <= WAIT_DHIT;`
70	23	robfinch	`if (isMove)`
71			`retstate <= MVN3;`
72			`else`
73			`retstate <= IFETCH;`
74	20	robfinch	`end`
75			`end`
76	21	robfinch	`else if (err_i) begin`
77			`lock_o <= 1'b0;`
78			`cyc_o <= 1'b0;`
79			`stb_o <= 1'b0;`
80			`we_o <= 1'b0;`
81			`sel_o <= 4'h0;`
82			`dat_o <= 32'h0;`
83			`state <= BUS_ERROR;`
84			`end`
85
86	20	robfinch

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [store.v] - Blame information for rev 25