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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [store.v] - Blame information for rev 33

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                            
// Memory store states
// The store states work for either eight bit or 32 bit mode              
// ============================================================================
//
// Stores always write through to memory, then optionally update the cache if
// there was a write hit.
STORE1:
        begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                we_o <= 1'b1;
                if (em || isStb) begin
                        case(wadr2LSB)
                        2'd0:   sel_o <= 4'b0001;
                        2'd1:   sel_o <= 4'b0010;
                        2'd2:   sel_o <= 4'b0100;
                        2'd3:   sel_o <= 4'b1000;
                        endcase
                end
                else
                        sel_o <= 4'hf;
                adr_o <= {wadr,2'b00};
                case(store_what)
                `STW_ACC:       dat_o <= acc;
                `STW_X:         dat_o <= x;
                `STW_Y:         dat_o <= y;
                `STW_PC:        dat_o <= pc;
                `STW_PC2:       dat_o <= pc + 32'd2;
                `STW_PCHWI:     dat_o <= pc+{30'b0,~hwi,1'b0};
                `STW_OPC:       dat_o <= opc;
                `STW_SR:        dat_o <= sr;
                `STW_RFA:       dat_o <= rfoa;
                `STW_RFA8:      dat_o <= {4{rfoa[7:0]}};
                `STW_A:         dat_o <= a;
                `STW_B:         dat_o <= b;
                `STW_CALC:      dat_o <= res;
`ifdef SUPPORT_EM8
                `STW_ACC8:      dat_o <= {4{acc8}};
                `STW_X8:        dat_o <= {4{x8}};
                `STW_Y8:        dat_o <= {4{y8}};
                `STW_Z8:        dat_o <= {4{8'h00}};
                `STW_PC3124:    dat_o <= {4{pc[31:24]}};
                `STW_PC2316:    dat_o <= {4{pc[23:16]}};
                `STW_PC158:             dat_o <= {4{pc[15:8]}};
                `STW_PC70:              dat_o <= {4{pc[7:0]}};
                `STW_SR70:              dat_o <= {4{sr8}};
`endif
                default:        dat_o <= wdat;
                endcase
`ifdef SUPPORT_DCACHE
                radr <= wadr;           // Do a cache read to test the hit
`endif
                state <= STORE2;
        end
 
// Terminal state for stores. Update the data cache if there was a cache hit.
// Clear any previously set lock status
STORE2:
        if (ack_i) begin
                wdat <= dat_o;
                if (isMove|isSts) begin
                        state <= MVN3;
                        retstate <= MVN3;
                end
                else begin
                        if (em) begin
                                state <= BYTE_IFETCH;
                                retstate <= BYTE_IFETCH;
                        end
                        else begin
                                state <= IFETCH;
                                retstate <= IFETCH;
                        end
                end
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                case(store_what)
                `STW_PC,`STW_PC2,`STW_PCHWI,`STW_OPC:
                        if (isBrk|isBusErr) begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_SR;
                                state <= STORE1;
                                retstate <= STORE1;
                        end
                `STW_SR:
                        if (isBrk|isBusErr) begin
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                retstate <= LOAD_MAC1;
                                radr <= vect[31:2];
                                ttrig <= 1'b0;
                                tf <= 1'b0;                     // turn off trace mode
                                im <= 1'b1;
                                em <= 1'b0;                     // make sure we process in native mode; we might have been called up during emulation mode
                        end
                `STW_RFA:
                        if (isPusha) begin
                                if (ir[11:8]==4'hF) begin
                                        state <= IFETCH;
                                        retstate <= IFETCH;
                                end
                                else begin
                                        state <= STORE1;
                                        retstate <= STORE1;
                                        radr <= isp_dec;
                                        wadr <= isp_dec;
                                        isp <= isp_dec;
                                end
                                ir[11:8] <= ir[11:8] + 4'd1;
                        end
`ifdef SUPPORT_EM8
                `STW_PC3124:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                store_what <= `STW_PC2316;
                                sp <= sp_dec;
                                state <= STORE1;
                        end
                `STW_PC2316:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                sp <= sp_dec;
                                store_what <= `STW_PC158;
                                state <= STORE1;
                        end
                `STW_PC158:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                sp <= sp_dec;
                                store_what <= `STW_PC70;
                                state <= STORE1;
                        end
                `STW_PC70:
                        begin
                                case({1'b0,ir[7:0]})
                                `BRK:   begin
                                                radr <= {spage[31:8],sp[7:2]};
                                                wadr <= {spage[31:8],sp[7:2]};
                                                radr2LSB <= sp[1:0];
                                                wadr2LSB <= sp[1:0];
                                                sp <= sp_dec;
                                                store_what <= `STW_SR70;
                                                state <= STORE1;
                                                end
                                `JSR:   begin
                                                pc <= ir[23:8];
                                                $display("setting pc=%h", ir[23:8]);
                                                end
                                `JSL:   begin
                                                pc <= ir[39:8];
                                                end
                                `JSR_INDX:
                                                begin
                                                state <= LOAD_MAC1;
                                                retstate <= LOAD_MAC1;
                                                load_what <= `PC_70;
                                                radr <= absx_address[31:2];
                                                radr2LSB <= absx_address[1:0];
                                                end
                                endcase
                        end
                `STW_SR70:
                        begin
                                if (ir[7:0]==`BRK) begin
                                        load_what <= `PC_70;
                                        state <= LOAD_MAC1;
                                        retstate <= LOAD_MAC1;
                                        pc[31:16] <= abs8[31:16];
                                        radr <= vect[31:2];
                                        radr2LSB <= vect[1:0];
                                        im <= hwi;
                                end
                        end
`endif
                default:
                        if (isJsrIndx) begin
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                retstate <= LOAD_MAC1;
                                radr <= ir[39:8] + x;
                        end
                        else if (isJsrInd) begin
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                retstate <= LOAD_MAC1;
                                radr <= ir[39:8];
                        end
                endcase
`ifdef SUPPORT_DCACHE
                if (!dhit && write_allocate) begin
                        state <= DCACHE1;
                end
`endif
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
`endif
 
 

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// Memory store states`
22			`// The store states work for either eight bit or 32 bit mode`
23			`// ============================================================================`
24			`//`
25			`// Stores always write through to memory, then optionally update the cache if`
26			`// there was a write hit.`
27			`STORE1:`
28			`begin`
29			`cyc_o <= 1'b1;`
30			`stb_o <= 1'b1;`
31			`we_o <= 1'b1;`
32	25	robfinch	`if (em \|\| isStb) begin`
33	20	robfinch	`case(wadr2LSB)`
34			`2'd0: sel_o <= 4'b0001;`
35			`2'd1: sel_o <= 4'b0010;`
36			`2'd2: sel_o <= 4'b0100;`
37			`2'd3: sel_o <= 4'b1000;`
38			`endcase`
39	25	robfinch	`end`
40	20	robfinch	`else`
41			`sel_o <= 4'hf;`
42			`adr_o <= {wadr,2'b00};`
43	30	robfinch	`case(store_what)`
44			`STW_ACC: dat_o <= acc;
45			`STW_X: dat_o <= x;
46			`STW_Y: dat_o <= y;
47			`STW_PC: dat_o <= pc;
48			`STW_PC2: dat_o <= pc + 32'd2;
49			`STW_PCHWI: dat_o <= pc+{30'b0,~hwi,1'b0};
50	32	robfinch	`STW_OPC: dat_o <= opc;
51	30	robfinch	`STW_SR: dat_o <= sr;
52			`STW_RFA: dat_o <= rfoa;
53			`STW_RFA8: dat_o <= {4{rfoa[7:0]}};
54			`STW_A: dat_o <= a;
55			`STW_B: dat_o <= b;
56	32	robfinch	`STW_CALC: dat_o <= res;
57	30	robfinch	`ifdef SUPPORT_EM8
58			`STW_ACC8: dat_o <= {4{acc8}};
59			`STW_X8: dat_o <= {4{x8}};
60			`STW_Y8: dat_o <= {4{y8}};
61	32	robfinch	`STW_Z8: dat_o <= {4{8'h00}};
62	30	robfinch	`STW_PC3124: dat_o <= {4{pc[31:24]}};
63			`STW_PC2316: dat_o <= {4{pc[23:16]}};
64			`STW_PC158: dat_o <= {4{pc[15:8]}};
65			`STW_PC70: dat_o <= {4{pc[7:0]}};
66			`STW_SR70: dat_o <= {4{sr8}};
67			`endif
68			`default: dat_o <= wdat;`
69			`endcase`
70			`ifdef SUPPORT_DCACHE
71	20	robfinch	`radr <= wadr; // Do a cache read to test the hit`
72	30	robfinch	`endif
73	20	robfinch	`state <= STORE2;`
74			`end`
75
76			`// Terminal state for stores. Update the data cache if there was a cache hit.`
77			`// Clear any previously set lock status`
78			`STORE2:`
79			`if (ack_i) begin`
80	30	robfinch	`wdat <= dat_o;`
81			`if (isMove\|isSts) begin`
82	23	robfinch	`state <= MVN3;`
83	30	robfinch	`retstate <= MVN3;`
84			`end`
85			`else begin`
86	32	robfinch	`if (em) begin`
87			`state <= BYTE_IFETCH;`
88			`retstate <= BYTE_IFETCH;`
89			`end`
90			`else begin`
91			`state <= IFETCH;`
92			`retstate <= IFETCH;`
93			`end`
94	30	robfinch	`end`
95	20	robfinch	`lock_o <= 1'b0;`
96			`cyc_o <= 1'b0;`
97			`stb_o <= 1'b0;`
98			`we_o <= 1'b0;`
99			`sel_o <= 4'h0;`
100			`adr_o <= 34'h0;`
101			`dat_o <= 32'h0;`
102	30	robfinch	`case(store_what)`
103	32	robfinch	`STW_PC,`STW_PC2,`STW_PCHWI,`STW_OPC:
104			`if (isBrk\|isBusErr) begin`
105	30	robfinch	`radr <= isp_dec;`
106			`wadr <= isp_dec;`
107			`isp <= isp_dec;`
108			store_what <= `STW_SR;
109			`state <= STORE1;`
110			`retstate <= STORE1;`
111			`end`
112			`STW_SR:
113	32	robfinch	`if (isBrk\|isBusErr) begin`
114	30	robfinch	load_what <= `PC_310;
115			`state <= LOAD_MAC1;`
116			`retstate <= LOAD_MAC1;`
117			`radr <= vect[31:2];`
118	32	robfinch	`ttrig <= 1'b0;`
119			`tf <= 1'b0; // turn off trace mode`
120			`im <= 1'b1;`
121	30	robfinch	`em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode`
122			`end`
123	32	robfinch	`STW_RFA:
124			`if (isPusha) begin`
125			`if (ir[11:8]==4'hF) begin`
126			`state <= IFETCH;`
127			`retstate <= IFETCH;`
128			`end`
129			`else begin`
130			`state <= STORE1;`
131			`retstate <= STORE1;`
132			`radr <= isp_dec;`
133			`wadr <= isp_dec;`
134			`isp <= isp_dec;`
135			`end`
136			`ir[11:8] <= ir[11:8] + 4'd1;`
137			`end`
138	30	robfinch	`ifdef SUPPORT_EM8
139			`STW_PC3124:
140			`begin`
141	32	robfinch	`radr <= {spage[31:8],sp[7:2]};`
142			`wadr <= {spage[31:8],sp[7:2]};`
143			`radr2LSB <= sp[1:0];`
144			`wadr2LSB <= sp[1:0];`
145	30	robfinch	store_what <= `STW_PC2316;
146	32	robfinch	`sp <= sp_dec;`
147	30	robfinch	`state <= STORE1;`
148			`end`
149			`STW_PC2316:
150			`begin`
151	32	robfinch	`radr <= {spage[31:8],sp[7:2]};`
152			`wadr <= {spage[31:8],sp[7:2]};`
153			`radr2LSB <= sp[1:0];`
154			`wadr2LSB <= sp[1:0];`
155			`sp <= sp_dec;`
156	30	robfinch	store_what <= `STW_PC158;
157			`state <= STORE1;`
158			`end`
159			`STW_PC158:
160			`begin`
161	32	robfinch	`radr <= {spage[31:8],sp[7:2]};`
162			`wadr <= {spage[31:8],sp[7:2]};`
163			`radr2LSB <= sp[1:0];`
164			`wadr2LSB <= sp[1:0];`
165			`sp <= sp_dec;`
166	30	robfinch	store_what <= `STW_PC70;
167			`state <= STORE1;`
168			`end`
169			`STW_PC70:
170			`begin`
171	32	robfinch	`case({1'b0,ir[7:0]})`
172			`BRK: begin
173			`radr <= {spage[31:8],sp[7:2]};`
174			`wadr <= {spage[31:8],sp[7:2]};`
175			`radr2LSB <= sp[1:0];`
176			`wadr2LSB <= sp[1:0];`
177			`sp <= sp_dec;`
178			store_what <= `STW_SR70;
179			`state <= STORE1;`
180			`end`
181			`JSR: begin
182			`pc <= ir[23:8];`
183			`$display("setting pc=%h", ir[23:8]);`
184			`end`
185			`JSL: begin
186			`pc <= ir[39:8];`
187			`end`
188			`JSR_INDX:
189			`begin`
190			`state <= LOAD_MAC1;`
191			`retstate <= LOAD_MAC1;`
192			load_what <= `PC_70;
193			`radr <= absx_address[31:2];`
194			`radr2LSB <= absx_address[1:0];`
195			`end`
196			`endcase`
197			`end`
198			`STW_SR70:
199			`begin`
200	30	robfinch	if (ir[7:0]==`BRK) begin
201	32	robfinch	load_what <= `PC_70;
202			`state <= LOAD_MAC1;`
203			`retstate <= LOAD_MAC1;`
204			`pc[31:16] <= abs8[31:16];`
205			`radr <= vect[31:2];`
206			`radr2LSB <= vect[1:0];`
207			`im <= hwi;`
208	30	robfinch	`end`
209			`end`
210			`endif
211	32	robfinch	`default:`
212			`if (isJsrIndx) begin`
213			load_what <= `PC_310;
214			`state <= LOAD_MAC1;`
215			`retstate <= LOAD_MAC1;`
216			`radr <= ir[39:8] + x;`
217			`end`
218			`else if (isJsrInd) begin`
219			load_what <= `PC_310;
220			`state <= LOAD_MAC1;`
221			`retstate <= LOAD_MAC1;`
222			`radr <= ir[39:8];`
223			`end`
224	30	robfinch	`endcase`
225			`ifdef SUPPORT_DCACHE
226	32	robfinch	`if (!dhit && write_allocate) begin`
227			`state <= DCACHE1;`
228	20	robfinch	`end`
229	30	robfinch	`endif
230	20	robfinch	`end`
231	30	robfinch	`ifdef SUPPORT_BERR
232	21	robfinch	`else if (err_i) begin`
233			`lock_o <= 1'b0;`
234			`cyc_o <= 1'b0;`
235			`stb_o <= 1'b0;`
236			`we_o <= 1'b0;`
237			`sel_o <= 4'h0;`
238			`dat_o <= 32'h0;`
239			`state <= BUS_ERROR;`
240			`end`
241	30	robfinch	`endif
242	21	robfinch
243	20	robfinch

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [store.v] - Blame information for rev 33