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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                            
// Memory store states
// The store states work for either eight bit or 32 bit mode              
// ============================================================================
//
// Stores always write through to memory, then optionally update the cache if
// there was a write hit.
STORE1:
        begin
                case(store_what)
                `STW_ACC:       wb_write(0,acc);
                `STW_X:         wb_write(0,x);
                `STW_Y:         wb_write(0,y);
                `STW_PC:        wb_write(0,pc);
                `STW_PC2:       wb_write(0,pc + 32'd2);
                `STW_PCHWI:     wb_write(0,pc+{30'b0,~hwi,1'b0});
                `STW_OPC:       wb_write(0,opc);
                `STW_SR:        wb_write(0,sr);
                `STW_RFA:       wb_write(0,rfoa);
                `STW_RFA8:      wb_write(1,{4{rfoa[7:0]}});
                `STW_A:         wb_write(0,a);
                `STW_B:         wb_write(0,b);
                `STW_CALC:      wb_write(0,res[31:0]);
`ifdef SUPPORT_EM8
                `STW_ACC8:      wb_write(1,{4{acc8}});
                `STW_X8:        wb_write(1,{4{x8}});
                `STW_Y8:        wb_write(1,{4{y8}});
                `STW_Z8:        wb_write(1,{4{8'h00}});
                `STW_PC3124:    wb_write(1,{4{pc[31:24]}});
                `STW_PC2316:    wb_write(1,{4{pc[23:16]}});
                `STW_PC158:             wb_write(1,{4{pc[15:8]}});
                `STW_PC70:              wb_write(1,{4{pc[7:0]}});
                `STW_SR70:              wb_write(1,{4{sr8}});
                `STW_DEF8:              wb_write(1,wdat);
`endif
                default:        wb_write(0,wdat);
                endcase
`ifdef SUPPORT_DCACHE
                radr <= wadr;           // Do a cache read to test the hit
`endif
                state <= STORE2;
        end
 
// Terminal state for stores. Update the data cache if there was a cache hit.
// Clear any previously set lock status
STORE2:
        // On a retry operation, restore the stack pointer which may have been
        // modified, then go back to the decode state to pick up original 
        // addresses and data. This doesn't work for block move/store
        if (rty_i) begin
                wb_nack();
                isp <= oisp;
                state <= DECODE;
        end
        else if (ack_i) begin
                wdat <= dat_o;
                if (isMove|isSts) begin
                        state <= MVN3;
                        retstate <= MVN3;
                end
                else begin
                        if (em) begin
                                state <= BYTE_IFETCH;
                                retstate <= BYTE_IFETCH;
                        end
                        else begin
                                state <= IFETCH;
                                retstate <= IFETCH;
                        end
                end
                lock_o <= 1'b0;
                wb_nack();
                case(store_what)
                `STW_PC,`STW_PC2,`STW_PCHWI,`STW_OPC:
                        if (isBrk|isBusErr) begin
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                isp <= isp_dec;
                                store_what <= `STW_SR;
                                state <= STORE1;
                                retstate <= STORE1;
                        end
                `STW_SR:
                        if (isBrk|isBusErr) begin
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                retstate <= LOAD_MAC1;
                                radr <= vect[33:2];
                                ttrig <= 1'b0;
                                tf <= 1'b0;                     // turn off trace mode
                                im <= 1'b1;
                                em <= 1'b0;                     // make sure we process in native mode; we might have been called up during emulation mode
                        end
                `STW_RFA:
                        if (isPusha) begin
                                if (ir[11:8]==4'hF) begin
                                        state <= IFETCH;
                                        retstate <= IFETCH;
                                end
                                else begin
                                        state <= STORE1;
                                        retstate <= STORE1;
                                        radr <= isp_dec;
                                        wadr <= isp_dec;
                                        isp <= isp_dec;
                                end
                                ir[11:8] <= ir[11:8] + 4'd1;
                        end
`ifdef SUPPORT_EM8
                `STW_PC3124:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                store_what <= `STW_PC2316;
                                sp <= sp_dec;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
                `STW_PC2316:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                sp <= sp_dec;
                                store_what <= `STW_PC158;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
                `STW_PC158:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                sp <= sp_dec;
                                store_what <= `STW_PC70;
                                retstate <= STORE1;
                                state <= STORE1;
                        end
                `STW_PC70:
                        begin
                                case({1'b0,ir[7:0]})
                                `BRK:   begin
                                                radr <= {spage[31:8],sp[7:2]};
                                                wadr <= {spage[31:8],sp[7:2]};
                                                radr2LSB <= sp[1:0];
                                                wadr2LSB <= sp[1:0];
                                                sp <= sp_dec;
                                                store_what <= `STW_SR70;
                                                retstate <= STORE1;
                                                state <= STORE1;
                                                end
                                `JSR:   begin
                                                pc[15:0] <= ir[23:8];
                                                end
                                `JSL:   begin
                                                pc <= ir[39:8];
                                                end
                                `JSR_INDX:
                                                begin
                                                state <= LOAD_MAC1;
                                                retstate <= LOAD_MAC1;
                                                load_what <= `PC_70;
                                                radr <= absx_address[31:2];
                                                radr2LSB <= absx_address[1:0];
                                                end
                                endcase
                        end
                `STW_SR70:
                        begin
                                if (ir[7:0]==`BRK) begin
                                        load_what <= `PC_70;
                                        state <= LOAD_MAC1;
                                        retstate <= LOAD_MAC1;
                                        pc[31:16] <= abs8[31:16];
                                        radr <= vect[33:2];
                                        radr2LSB <= vect[1:0];
                                        im <= hwi;
                                end
                        end
`endif
                default:
                        if (isJsrIndx) begin
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                retstate <= LOAD_MAC1;
                                radr <= ir[39:8] + x;
                        end
                        else if (isJsrInd) begin
                                load_what <= `PC_310;
                                state <= LOAD_MAC1;
                                retstate <= LOAD_MAC1;
                                radr <= ir[39:8];
                        end
                endcase
`ifdef SUPPORT_DCACHE
                if (!dhit && write_allocate) begin
                        state <= DCACHE1;
                end
`endif
        end
`ifdef SUPPORT_BERR
        else if (err_i) begin
                lock_o <= 1'b0;
                wb_nack();
                if (em | isStb)
                        derr_address <= adr_o[31:0];
                else
                        derr_address <= adr_o[33:2];
                intno <= 9'd508;
                state <= BUS_ERROR;
        end
`endif

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// Memory store states`
22			`// The store states work for either eight bit or 32 bit mode`
23			`// ============================================================================`
24			`//`
25			`// Stores always write through to memory, then optionally update the cache if`
26			`// there was a write hit.`
27			`STORE1:`
28			`begin`
29	30	robfinch	`case(store_what)`
30	35	robfinch	`STW_ACC: wb_write(0,acc);
31			`STW_X: wb_write(0,x);
32			`STW_Y: wb_write(0,y);
33			`STW_PC: wb_write(0,pc);
34			`STW_PC2: wb_write(0,pc + 32'd2);
35			`STW_PCHWI: wb_write(0,pc+{30'b0,~hwi,1'b0});
36			`STW_OPC: wb_write(0,opc);
37			`STW_SR: wb_write(0,sr);
38			`STW_RFA: wb_write(0,rfoa);
39			`STW_RFA8: wb_write(1,{4{rfoa[7:0]}});
40			`STW_A: wb_write(0,a);
41			`STW_B: wb_write(0,b);
42			`STW_CALC: wb_write(0,res[31:0]);
43	30	robfinch	`ifdef SUPPORT_EM8
44	35	robfinch	`STW_ACC8: wb_write(1,{4{acc8}});
45			`STW_X8: wb_write(1,{4{x8}});
46			`STW_Y8: wb_write(1,{4{y8}});
47			`STW_Z8: wb_write(1,{4{8'h00}});
48			`STW_PC3124: wb_write(1,{4{pc[31:24]}});
49			`STW_PC2316: wb_write(1,{4{pc[23:16]}});
50			`STW_PC158: wb_write(1,{4{pc[15:8]}});
51			`STW_PC70: wb_write(1,{4{pc[7:0]}});
52			`STW_SR70: wb_write(1,{4{sr8}});
53			`STW_DEF8: wb_write(1,wdat);
54	30	robfinch	`endif
55	35	robfinch	`default: wb_write(0,wdat);`
56	30	robfinch	`endcase`
57			`ifdef SUPPORT_DCACHE
58	20	robfinch	`radr <= wadr; // Do a cache read to test the hit`
59	30	robfinch	`endif
60	20	robfinch	`state <= STORE2;`
61			`end`
62
63			`// Terminal state for stores. Update the data cache if there was a cache hit.`
64			`// Clear any previously set lock status`
65			`STORE2:`
66	35	robfinch	`// On a retry operation, restore the stack pointer which may have been`
67			`// modified, then go back to the decode state to pick up original`
68			`// addresses and data. This doesn't work for block move/store`
69			`if (rty_i) begin`
70			`wb_nack();`
71			`isp <= oisp;`
72			`state <= DECODE;`
73			`end`
74			`else if (ack_i) begin`
75	30	robfinch	`wdat <= dat_o;`
76			`if (isMove\|isSts) begin`
77	23	robfinch	`state <= MVN3;`
78	30	robfinch	`retstate <= MVN3;`
79			`end`
80			`else begin`
81	32	robfinch	`if (em) begin`
82			`state <= BYTE_IFETCH;`
83			`retstate <= BYTE_IFETCH;`
84			`end`
85			`else begin`
86			`state <= IFETCH;`
87			`retstate <= IFETCH;`
88			`end`
89	30	robfinch	`end`
90	20	robfinch	`lock_o <= 1'b0;`
91	35	robfinch	`wb_nack();`
92	30	robfinch	`case(store_what)`
93	32	robfinch	`STW_PC,`STW_PC2,`STW_PCHWI,`STW_OPC:
94			`if (isBrk\|isBusErr) begin`
95	30	robfinch	`radr <= isp_dec;`
96			`wadr <= isp_dec;`
97			`isp <= isp_dec;`
98			store_what <= `STW_SR;
99			`state <= STORE1;`
100			`retstate <= STORE1;`
101			`end`
102			`STW_SR:
103	32	robfinch	`if (isBrk\|isBusErr) begin`
104	30	robfinch	load_what <= `PC_310;
105			`state <= LOAD_MAC1;`
106			`retstate <= LOAD_MAC1;`
107	35	robfinch	`radr <= vect[33:2];`
108	32	robfinch	`ttrig <= 1'b0;`
109			`tf <= 1'b0; // turn off trace mode`
110			`im <= 1'b1;`
111	30	robfinch	`em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode`
112			`end`
113	32	robfinch	`STW_RFA:
114			`if (isPusha) begin`
115			`if (ir[11:8]==4'hF) begin`
116			`state <= IFETCH;`
117			`retstate <= IFETCH;`
118			`end`
119			`else begin`
120			`state <= STORE1;`
121			`retstate <= STORE1;`
122			`radr <= isp_dec;`
123			`wadr <= isp_dec;`
124			`isp <= isp_dec;`
125			`end`
126			`ir[11:8] <= ir[11:8] + 4'd1;`
127			`end`
128	30	robfinch	`ifdef SUPPORT_EM8
129			`STW_PC3124:
130			`begin`
131	32	robfinch	`radr <= {spage[31:8],sp[7:2]};`
132			`wadr <= {spage[31:8],sp[7:2]};`
133			`radr2LSB <= sp[1:0];`
134			`wadr2LSB <= sp[1:0];`
135	30	robfinch	store_what <= `STW_PC2316;
136	32	robfinch	`sp <= sp_dec;`
137	35	robfinch	`retstate <= STORE1;`
138	30	robfinch	`state <= STORE1;`
139			`end`
140			`STW_PC2316:
141			`begin`
142	32	robfinch	`radr <= {spage[31:8],sp[7:2]};`
143			`wadr <= {spage[31:8],sp[7:2]};`
144			`radr2LSB <= sp[1:0];`
145			`wadr2LSB <= sp[1:0];`
146			`sp <= sp_dec;`
147	30	robfinch	store_what <= `STW_PC158;
148	35	robfinch	`retstate <= STORE1;`
149	30	robfinch	`state <= STORE1;`
150			`end`
151			`STW_PC158:
152			`begin`
153	32	robfinch	`radr <= {spage[31:8],sp[7:2]};`
154			`wadr <= {spage[31:8],sp[7:2]};`
155			`radr2LSB <= sp[1:0];`
156			`wadr2LSB <= sp[1:0];`
157			`sp <= sp_dec;`
158	30	robfinch	store_what <= `STW_PC70;
159	35	robfinch	`retstate <= STORE1;`
160	30	robfinch	`state <= STORE1;`
161			`end`
162			`STW_PC70:
163			`begin`
164	32	robfinch	`case({1'b0,ir[7:0]})`
165			`BRK: begin
166			`radr <= {spage[31:8],sp[7:2]};`
167			`wadr <= {spage[31:8],sp[7:2]};`
168			`radr2LSB <= sp[1:0];`
169			`wadr2LSB <= sp[1:0];`
170			`sp <= sp_dec;`
171			store_what <= `STW_SR70;
172	35	robfinch	`retstate <= STORE1;`
173	32	robfinch	`state <= STORE1;`
174			`end`
175			`JSR: begin
176	35	robfinch	`pc[15:0] <= ir[23:8];`
177	32	robfinch	`end`
178			`JSL: begin
179			`pc <= ir[39:8];`
180			`end`
181			`JSR_INDX:
182			`begin`
183			`state <= LOAD_MAC1;`
184			`retstate <= LOAD_MAC1;`
185			load_what <= `PC_70;
186			`radr <= absx_address[31:2];`
187			`radr2LSB <= absx_address[1:0];`
188			`end`
189			`endcase`
190			`end`
191			`STW_SR70:
192			`begin`
193	30	robfinch	if (ir[7:0]==`BRK) begin
194	32	robfinch	load_what <= `PC_70;
195			`state <= LOAD_MAC1;`
196			`retstate <= LOAD_MAC1;`
197			`pc[31:16] <= abs8[31:16];`
198	35	robfinch	`radr <= vect[33:2];`
199	32	robfinch	`radr2LSB <= vect[1:0];`
200			`im <= hwi;`
201	30	robfinch	`end`
202			`end`
203			`endif
204	32	robfinch	`default:`
205			`if (isJsrIndx) begin`
206			load_what <= `PC_310;
207			`state <= LOAD_MAC1;`
208			`retstate <= LOAD_MAC1;`
209			`radr <= ir[39:8] + x;`
210			`end`
211			`else if (isJsrInd) begin`
212			load_what <= `PC_310;
213			`state <= LOAD_MAC1;`
214			`retstate <= LOAD_MAC1;`
215			`radr <= ir[39:8];`
216			`end`
217	30	robfinch	`endcase`
218			`ifdef SUPPORT_DCACHE
219	32	robfinch	`if (!dhit && write_allocate) begin`
220			`state <= DCACHE1;`
221	20	robfinch	`end`
222	30	robfinch	`endif
223	20	robfinch	`end`
224	30	robfinch	`ifdef SUPPORT_BERR
225	21	robfinch	`else if (err_i) begin`
226			`lock_o <= 1'b0;`
227	35	robfinch	`wb_nack();`
228			`if (em \| isStb)`
229			`derr_address <= adr_o[31:0];`
230			`else`
231			`derr_address <= adr_o[33:2];`
232			`intno <= 9'd508;`
233	21	robfinch	`state <= BUS_ERROR;`
234			`end`
235	30	robfinch	`endif

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [store.v] - Blame information for rev 35