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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [wb_task.v] - Blame information for rev 37

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Line No. Rev Author Line
1 35 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2013  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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task wb_burst;
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input [5:0] len;
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input [33:0] adr;
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begin
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        bte_o <= 2'b00;
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        cti_o <= 3'b001;
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        bl_o <= len;
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        cyc_o <= 1'b1;
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        stb_o <= 1'b1;
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        sel_o <= 4'hF;
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        adr_o <= adr;
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end
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endtask
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task wb_read;
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input [33:0] adr;
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begin
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        cyc_o <= 1'b1;
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        stb_o <= 1'b1;
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        sel_o <= 4'hF;
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        adr_o <= adr;
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end
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endtask
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task wb_write;
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input byt;
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input [31:0] dat;
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begin
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        cyc_o <= 1'b1;
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        stb_o <= 1'b1;
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        we_o <= 1'b1;
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        if (byt) begin
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                case(wadr2LSB)
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                2'd0:   sel_o <= 4'b0001;
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                2'd1:   sel_o <= 4'b0010;
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                2'd2:   sel_o <= 4'b0100;
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                2'd3:   sel_o <= 4'b1000;
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                endcase
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        end
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        else
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                sel_o <= 4'hf;
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        adr_o <= {wadr,2'b00};
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        dat_o <= dat;
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end
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endtask
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task wb_nack;
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begin
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        cti_o <= 3'b000;
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        bl_o <= 6'd0;
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        cyc_o <= 1'b0;
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        stb_o <= 1'b0;
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        sel_o <= 4'h0;
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        we_o <= 1'b0;
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        adr_o <= 34'd0;
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        dat_o <= 32'd0;
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end
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endtask

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