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[/] [rtf68ksys/] [trunk/] [rtl/] [verilog/] [HVCounter.v] - Blame information for rev 2

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1 2 robfinch
// ============================================================================
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//      2011  Robert Finch
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//      robfinch@<remove>sympatico.ca
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//
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// HVCounter.v
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// Horizontal / Vertical counter:
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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// horizontal pixel prescale counter
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// Each pixel may be multiple clocks wide
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//
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// 37 slices / 64 LUTs / 161.525 MHz
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// 28 ff's / 1 Mult
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module HVCounter(
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        rst, vclk, pixcce, sync, cnt_offs, pixsz, maxpix, nxt_pix, pos, nxt_pos, ctr
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);
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input rst;
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input vclk;                             // video clock
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input pixcce;                   // pixel counter clock enable
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input sync;                             // synchronization input (eol or eof)
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input [11:0] cnt_offs;   // counter offset: top or left of display area
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input [3:0] pixsz;               // size of a pixel in video clock
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input [4:0] maxpix;              // maximum pixels for width / height of character
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output nxt_pix;                 // when the next pixel will happen
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output [11:0] pos;               // current row or column position
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output nxt_pos;                 // flag: when the row or column is about to change
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output [11:0] ctr;               // counter output
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reg [11:0] pos;
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reg [11:0] ctr;
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reg nxt_pix;
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wire [11:0] ctr1;
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wire nxp;
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reg [23:0] x4096;
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// Lookup reciprocal of number of pixels per character
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// - used to calculate the column position
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reg [11:0] inv;
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always @(posedge vclk)
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        case(maxpix)
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        5'd00:  inv <= 12'd4095;
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        5'd01:  inv <= 12'd2048;
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        5'd02:  inv <= 12'd1365;
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        5'd03:  inv <= 12'd1024;
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        5'd04:  inv <= 12'd0819;
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        5'd05:  inv <= 12'd0683;
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        5'd06:  inv <= 12'd0585;
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        5'd07:  inv <= 12'd0512;
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        5'd08:  inv <= 12'd0455;
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        5'd09:  inv <= 12'd0409;
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        5'd10:  inv <= 12'd0372;
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        5'd11:  inv <= 12'd0341;
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        5'd12:  inv <= 12'd0315;
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        5'd13:  inv <= 12'd0292;
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        5'd14:  inv <= 12'd0273;
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        5'd15:  inv <= 12'd0256;
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        5'd16:  inv <= 12'd0240;
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        5'd17:  inv <= 12'd0227;
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        5'd18:  inv <= 12'd0215;
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        5'd19:  inv <= 12'd0204;
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        5'd20:  inv <= 12'd0195;
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        5'd21:  inv <= 12'd0186;
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        5'd22:  inv <= 12'd0178;
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        5'd23:  inv <= 12'd0170;
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        5'd24:  inv <= 12'd0163;
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        5'd25:  inv <= 12'd0157;
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        5'd26:  inv <= 12'd0151;
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        5'd27:  inv <= 12'd0146;
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        5'd28:  inv <= 12'd0141;
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        5'd29:  inv <= 12'd0136;
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        5'd30:  inv <= 12'd0132;
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        5'd31:  inv <= 12'd0128;
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        endcase
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// Calculate character position
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// - divide the raw count by the number of pixels per character
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// - done by multiplying by the reciprocal
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always @(posedge vclk)
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        x4096 <= ctr * inv;
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always @(x4096)
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        pos <= x4096[23:12];
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always @(posedge vclk)          // pipeline delay
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        ctr <= ctr1;
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always @(posedge vclk)
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        nxt_pix <= nxp;
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// Pixel width counter
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// Controls number of clock cycles per pixel
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VT163 #(4) u1
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(
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        .clk(vclk),
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        .clr_n(!rst),
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        .ent(pixcce),
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        .enp(1'b1),
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        .ld_n(!sync & !nxp),            // synchronize count to start of scan
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        .d(4'hF-pixsz),
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        .q(),
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        .rco(nxp)
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);
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// Pixel counter
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// - raw pixel count
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// - just increments every time the nxt_pix signal is active
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// - synchronized to the end-of-line or end-of-frame signal
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VT163 #(12) u2
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(
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        .clk(vclk),
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        .clr_n(!rst),
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        .ent(nxp),
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        .enp(1'b1),
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        .ld_n(!sync),                                   // synchronize count to start of scan
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        .d(12'h000-cnt_offs),
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        .q(ctr1),
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        .rco()
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);
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// Detect when the position changes
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// - compare current pos to previous pos when the position might change
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change_det #(12) u3
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(
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        .rst(rst),
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        .clk(vclk),
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        .ce(nxt_pix),
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        .i(pos),
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        .cd(nxt_pos)
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);
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endmodule

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