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robfinch |
//=============================================================================
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// 2007,2010 Robert Finch
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// robfinch@FPGAfield.ca
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//
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// PSG16.v
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// 4 Channel ADSR sound generator
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//
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// This source code is available only for veiwing, testing and evaluation
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// purposes. Any commercial use requires a license. This copyright
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// statement and disclaimer must remain present in the file.
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//
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//
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// NO WARRANTY.
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// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
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// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
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// Work.
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//
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// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
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// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
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// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
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//
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// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
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// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
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// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
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// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
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// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
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//
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//
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// Registers
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// 0 ffffffff ffffffff freq [15:0]
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// 1 ----pppp pppppppp pulse width [11:0]
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// 2 trsg--fo -vvvvv-- test, ringmod, sync, gate, filter, output, voice type
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// vvvvv
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// wnpst
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// 3 -------- -------- reserved
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// 4 aaaaaaaa aaaaaaaa attack
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// 5 ----dddd dddddddd decay
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// 6 -------- ssssssss sustain
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// 7 ----rrrr rrrrrrrr release
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// ...
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// 64 -------- ----vvvv volume (0-15)
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// 65 nnnnnnnn nnnnnnnn osc3 oscillator 3
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// 66 -------- nnnnnnnn env3 envelope 3
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// 67
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// 68 aa------ -------- wave table address a15-14
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// 69 aaaaaaaa aaaaaaaa wave table address a31-16
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//
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// 80-87 s---kkkk kkkkkkkk filter coefficients
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// 88-96 -------- -------- reserved for more filter coefficients
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//
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//
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// Spartan3
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// Webpack 12.3 xc3s1200e-4fg320
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// 1290 LUTs / 893 slices / 69.339 MHz
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// 1 Multipliers
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//=============================================================================
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module PSG16(rst_i, clk_i, cyc_i, stb_i, ack_o, we_i, sel_i, adr_i, dat_i, dat_o,
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vol_o, bg,
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m_cyc_o, m_stb_o, m_ack_i, m_we_o, m_sel_o, m_adr_o, m_dat_i, o
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);
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parameter pClkDivide = 66;
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// WISHBONE SYSCON
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input rst_i;
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input clk_i; // system clock
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// WISHBONE SLAVE
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input cyc_i; // cycle valid
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input stb_i; // circuit select
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output ack_o;
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input we_i; // write
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input [1:0] sel_i; // byte selects
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input [43:0] adr_i; // address input
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input [15:0] dat_i; // data input
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output [15:0] dat_o; // data output
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// WISHBONE MASTER
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output m_cyc_o; // bus request
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output m_stb_o; // strobe output
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input m_ack_i;
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output m_we_o; // write enable (always inactive)
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output [ 1:0] m_sel_o; // byte lane selects
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output [43:0] m_adr_o; // wave table address
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input [11:0] m_dat_i; // wave table data input
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output vol_o;
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input bg; // bus grant
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output [11:0] o;
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// I/O registers
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reg [15:0] dat_o;
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reg vol_o;
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reg [43:0] m_adr_o;
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reg [3:0] test; // test (enable note generator)
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reg [4:0] vt [3:0]; // voice type
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reg [15:0] freq0, freq1, freq2, freq3; // frequency control
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reg [11:0] pw0, pw1, pw2, pw3; // pulse width control
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reg [3:0] gate;
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reg [15:0] attack0, attack1, attack2, attack3;
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reg [11:0] decay0, decay1, decay2, decay3;
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reg [7:0] sustain0, sustain1, sustain2, sustain3;
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reg [11:0] relese0, relese1, relese2, relese3;
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reg [3:0] sync;
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reg [3:0] ringmod;
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reg [3:0] outctrl;
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reg [3:0] filt; // 1 = output goes to filter
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wire [23:0] acc0, acc1, acc2, acc3;
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reg [3:0] volume; // master volume
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wire [11:0] ngo; // not generator output
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wire [7:0] env; // envelope generator output
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wire [7:0] env3;
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wire [7:0] ibr;
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wire [7:0] ibg;
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wire [21:0] out1;
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wire [21:0] out3;
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wire [19:0] out4;
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wire [21:0] filtin1; // FIR filter input
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wire [14:0] filt_o; // FIR filter output
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wire cs = cyc_i && stb_i && (adr_i[43:8]==36'hFFF_FFD4_00);
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assign m_cyc_o = |ibr & ~bg;
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assign m_stb_o = m_cyc_o;
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assign m_we_o = 1'b0;
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assign m_sel_o = {m_cyc_o,m_cyc_o};
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assign ack_o = cs;
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wire my_ack = m_ack_i;
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// write to registers
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always @(posedge clk_i)
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begin
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if (rst_i) begin
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freq0 <= 0;
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freq1 <= 0;
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freq2 <= 0;
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freq3 <= 0;
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pw0 <= 0;
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pw1 <= 0;
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pw2 <= 0;
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pw3 <= 0;
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test <= 0;
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vt[0] <= 0;
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vt[1] <= 0;
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vt[2] <= 0;
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vt[3] <= 0;
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gate <= 0;
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outctrl <= 0;
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filt <= 0;
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attack0 <= 0;
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attack1 <= 0;
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attack2 <= 0;
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attack3 <= 0;
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decay0 <= 0;
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sustain0 <= 0;
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relese0 <= 0;
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decay1 <= 0;
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sustain1 <= 0;
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relese1 <= 0;
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decay2 <= 0;
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sustain2 <= 0;
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relese2 <= 0;
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decay3 <= 0;
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sustain3 <= 0;
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relese3 <= 0;
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sync <= 0;
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ringmod <= 0;
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volume <= 0;
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m_adr_o[31:14] <= 18'b0000_0000_0000_0011_10; // 00038000
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end
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else begin
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if (ack_o & we_i) begin
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case(adr_i[7:1])
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7'd0:
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begin
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if (sel_i[0]) freq0[ 7:0] <= dat_i[ 7:0];
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if (sel_i[1]) freq0[15:8] <= dat_i[15:8];
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end
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7'd1:
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begin
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if (sel_i[0]) pw0[ 7:0] <= dat_i[ 7:0];
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if (sel_i[1]) pw0[11:8] <= dat_i[11:8];
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end
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7'd2: begin
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if (sel_i[0]) vt[0] <= dat_i[6:2];
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if (sel_i[1]) begin
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outctrl[0] <= dat_i[8];
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filt[0] <= dat_i[9];
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gate[0] <= dat_i[12];
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sync[0] <= dat_i[13];
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ringmod[0] <= dat_i[14];
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test[0] <= dat_i[15];
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end
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end
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7'd3: ;
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7'd4: attack0 <= dat_i;
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7'd5: decay0 <= dat_i;
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7'd6: if (sel_i[0]) sustain0 <= dat_i;
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7'd7: relese0 <= dat_i;
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7'd8:
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begin
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if (sel_i[0]) freq1[ 7:0] <= dat_i[ 7:0];
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if (sel_i[1]) freq1[15:8] <= dat_i[15:8];
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end
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7'd9:
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begin
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if (sel_i[0]) pw1[ 7:0] <= dat_i[ 7:0];
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if (sel_i[1]) pw1[11:8] <= dat_i[11:8];
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end
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7'd10: begin
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if (sel_i[0]) vt[1] <= dat_i[6:2];
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if (sel_i[1]) begin
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outctrl[1] <= dat_i[8];
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filt[1] <= dat_i[9];
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gate[1] <= dat_i[12];
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sync[1] <= dat_i[13];
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ringmod[1] <= dat_i[14];
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test[1] <= dat_i[15];
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end
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end
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7'd11: ;
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7'd12: attack1 <= dat_i;
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7'd13: decay1 <= dat_i;
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7'd14: if (sel_i[0]) sustain1 <= dat_i;
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7'd15: relese1 <= dat_i;
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7'd16:
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begin
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if (sel_i[0]) freq2[ 7:0] <= dat_i[ 7:0];
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if (sel_i[1]) freq2[15:8] <= dat_i[15:8];
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end
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7'd17:
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begin
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if (sel_i[0]) pw2[ 7:0] <= dat_i[ 7:0];
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if (sel_i[1]) pw2[11:8] <= dat_i[11:8];
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end
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7'd18: begin
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if (sel_i[0]) vt[2] <= dat_i[6:2];
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if (sel_i[1]) begin
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outctrl[2] <= dat_i[8];
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filt[2] <= dat_i[9];
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gate[2] <= dat_i[12];
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sync[2] <= dat_i[5];
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outctrl[0] <= dat_i[13];
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ringmod[2] <= dat_i[14];
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test[2] <= dat_i[15];
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end
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end
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7'd19: ;
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7'd20: attack2 <= dat_i;
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7'd21: decay2 <= dat_i;
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| 254 |
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7'd22: if (sel_i[0]) sustain2 <= dat_i;
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| 255 |
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7'd23: relese2 <= dat_i;
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| 256 |
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| 257 |
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7'd24:
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| 258 |
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begin
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| 259 |
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if (sel_i[0]) freq3[ 7:0] <= dat_i[ 7:0];
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| 260 |
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if (sel_i[1]) freq3[15:8] <= dat_i[15:8];
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| 261 |
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end
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| 262 |
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7'd25:
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| 263 |
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begin
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| 264 |
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if (sel_i[0]) pw3[ 7:0] <= dat_i[ 7:0];
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if (sel_i[1]) pw3[11:8] <= dat_i[11:8];
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| 266 |
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end
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| 267 |
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7'd26: begin
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| 268 |
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if (sel_i[0]) vt[3] <= dat_i[6:2];
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| 269 |
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if (sel_i[1]) begin
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| 270 |
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outctrl[3] <= dat_i[8];
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| 271 |
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filt[3] <= dat_i[9];
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| 272 |
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gate[3] <= dat_i[12];
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| 273 |
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sync[3] <= dat_i[13];
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| 274 |
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ringmod[3] <= dat_i[14];
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| 275 |
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test[3] <= dat_i[15];
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| 276 |
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end
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| 277 |
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end
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| 278 |
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7'd27: ;
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| 279 |
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7'd28: attack3 <= dat_i;
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| 280 |
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7'd29: decay3 <= dat_i;
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| 281 |
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7'd30: if (sel_i[0]) sustain3 <= dat_i;
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| 282 |
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7'd31: relese3 <= dat_i;
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| 283 |
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| 284 |
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7'd64: if (sel_i[0]) volume <= dat_i[3:0];
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| 285 |
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| 286 |
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7'd68: begin
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| 287 |
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if (sel_i[1]) m_adr_o[15:14] <= dat_i[15:14];
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| 288 |
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end
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| 289 |
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7'd69:
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| 290 |
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begin
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| 291 |
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if (sel_i[0]) m_adr_o[23:16] <= dat_i[ 7:0];
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| 292 |
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if (sel_i[1]) m_adr_o[31:24] <= dat_i[15:8];
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| 293 |
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end
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| 294 |
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7'd70: begin
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| 295 |
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if (sel_i[0]) m_adr_o[39:32] <= dat_i[ 7:0];
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| 296 |
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if (sel_i[1]) m_adr_o[43:40] <= dat_i[11:8];
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| 297 |
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end
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| 298 |
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default: ;
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| 299 |
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endcase
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| 300 |
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end
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| 301 |
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end
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| 302 |
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end
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| 303 |
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| 304 |
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| 305 |
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always @(adr_i or acc3 or env3 or cs)
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| 306 |
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begin
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| 307 |
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if (cs) begin
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| 308 |
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case(adr_i[6:0])
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| 309 |
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7'd65: begin
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| 310 |
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vol_o <= 1'b1;
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| 311 |
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dat_o <= acc3[23:8];
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| 312 |
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end
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| 313 |
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7'd66: begin
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| 314 |
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vol_o <= 1'b1;
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| 315 |
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dat_o <= env3;
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| 316 |
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end
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| 317 |
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default: begin
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| 318 |
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dat_o <= env3;
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| 319 |
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vol_o <= 1'b0;
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| 320 |
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end
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| 321 |
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endcase
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| 322 |
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end
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| 323 |
|
|
else begin
|
| 324 |
|
|
dat_o <= 16'b0;
|
| 325 |
|
|
vol_o <= 1'b0;
|
| 326 |
|
|
end
|
| 327 |
|
|
end
|
| 328 |
|
|
|
| 329 |
|
|
wire [3:0] ibg1 = ibg & {4{bg}};
|
| 330 |
|
|
wire [11:0] alow;
|
| 331 |
|
|
|
| 332 |
|
|
// set wave table output address
|
| 333 |
|
|
always @(ibg1 or acc1 or acc0 or acc2 or acc3 or alow)
|
| 334 |
|
|
begin
|
| 335 |
|
|
m_adr_o[13:12] <= {ibg1[2]|ibg1[3],ibg1[1]|ibg1[3]};
|
| 336 |
|
|
m_adr_o[11:0] <= alow;
|
| 337 |
|
|
end
|
| 338 |
|
|
|
| 339 |
|
|
mux4to1 #(12) u11
|
| 340 |
|
|
(
|
| 341 |
|
|
.e(1'b1),
|
| 342 |
|
|
.s(m_adr_o[13:12]),
|
| 343 |
|
|
.i0({acc0[23:13],1'b0}),
|
| 344 |
|
|
.i1({acc1[23:13],1'b0}),
|
| 345 |
|
|
.i2({acc2[23:13],1'b0}),
|
| 346 |
|
|
.i3({acc3[23:13],1'b0}),
|
| 347 |
|
|
.z(alow)
|
| 348 |
|
|
);
|
| 349 |
|
|
|
| 350 |
|
|
// This counter controls channel multiplexing and the base
|
| 351 |
|
|
// operating frequency.
|
| 352 |
|
|
wire [7:0] cnt;
|
| 353 |
|
|
counter #(8) u1
|
| 354 |
|
|
(
|
| 355 |
|
|
.rst(rst_i),
|
| 356 |
|
|
.clk(clk_i),
|
| 357 |
|
|
.ce(1'b1),
|
| 358 |
|
|
.ld(cnt!=pClkDivide),
|
| 359 |
|
|
.d(8'd1),
|
| 360 |
|
|
.q(cnt)
|
| 361 |
|
|
);
|
| 362 |
|
|
|
| 363 |
|
|
// channel select signal
|
| 364 |
|
|
wire [1:0] sel = cnt[1:0];
|
| 365 |
|
|
|
| 366 |
|
|
|
| 367 |
|
|
// bus arbitrator for wave table access
|
| 368 |
|
|
wire [2:0] bgn;
|
| 369 |
|
|
PSGBusArb u2
|
| 370 |
|
|
(
|
| 371 |
|
|
.rst(rst_i),
|
| 372 |
|
|
.clk(clk_i),
|
| 373 |
|
|
.ce(1'b1),
|
| 374 |
|
|
.ack(1'b1), .seln(bgn),
|
| 375 |
|
|
.req0(ibr[0]), .req1(ibr[1]), .req2(ibr[2]), .req3(ibr[3]),
|
| 376 |
|
|
.sel0(ibg[0]), .sel1(ibg[1]), .sel2(ibg[2]), .sel3(ibg[3]),
|
| 377 |
|
|
.req4(1'b0), .req5(1'b0), .req6(1'b0), .req7(1'b0),
|
| 378 |
|
|
.sel4(), .sel5(), .sel6(), .sel7()
|
| 379 |
|
|
);
|
| 380 |
|
|
|
| 381 |
|
|
// note generator - multi-channel
|
| 382 |
|
|
PSGNoteGen u3
|
| 383 |
|
|
(
|
| 384 |
|
|
.rst(rst_i), .clk(clk_i),
|
| 385 |
|
|
.cnt(cnt), .br(ibr), .bg(ibg1), .ack(my_ack), .bgn(bgn),
|
| 386 |
|
|
.test(test),
|
| 387 |
|
|
.vt0(vt[0]), .vt1(vt[1]), .vt2(vt[2]), .vt3(vt[3]),
|
| 388 |
|
|
.freq0(freq0), .freq1(freq1), .freq2(freq2), .freq3(freq3),
|
| 389 |
|
|
.pw0(pw0), .pw1(pw1), .pw2(pw2), .pw3(pw3),
|
| 390 |
|
|
.acc0(acc0), .acc1(acc1), .acc2(acc2), .acc3(acc3),
|
| 391 |
|
|
.wave(m_dat_i),
|
| 392 |
|
|
.sync(sync),
|
| 393 |
|
|
.ringmod(ringmod),
|
| 394 |
|
|
.o(ngo)
|
| 395 |
|
|
);
|
| 396 |
|
|
|
| 397 |
|
|
// envelope generator - multi-channel
|
| 398 |
|
|
PSGEnvGen u4
|
| 399 |
|
|
(
|
| 400 |
|
|
.rst(rst_i),
|
| 401 |
|
|
.clk(clk_i),
|
| 402 |
|
|
.cnt(cnt),
|
| 403 |
|
|
.gate(gate),
|
| 404 |
|
|
.attack0(attack0), .attack1(attack1), .attack2(attack2), .attack3(attack3),
|
| 405 |
|
|
.decay0(decay0), .decay1(decay1), .decay2(decay2), .decay3(decay3),
|
| 406 |
|
|
.sustain0(sustain0), .sustain1(sustain1), .sustain2(sustain2), .sustain3(sustain3),
|
| 407 |
|
|
.relese0(relese0), .relese1(relese1), .relese2(relese2), .relese3(relese3),
|
| 408 |
|
|
.o(env)
|
| 409 |
|
|
);
|
| 410 |
|
|
|
| 411 |
|
|
// shape output according to envelope
|
| 412 |
|
|
PSGShaper u5
|
| 413 |
|
|
(
|
| 414 |
|
|
.clk_i(clk_i),
|
| 415 |
|
|
.ce(1'b1),
|
| 416 |
|
|
.tgi(ngo),
|
| 417 |
|
|
.env(env),
|
| 418 |
|
|
.o(out2)
|
| 419 |
|
|
);
|
| 420 |
|
|
|
| 421 |
|
|
// Sum the channels not going to the filter
|
| 422 |
|
|
PSGChannelSummer u6
|
| 423 |
|
|
(
|
| 424 |
|
|
.clk_i(clk_i),
|
| 425 |
|
|
.cnt(cnt),
|
| 426 |
|
|
.outctrl(outctrl),
|
| 427 |
|
|
.tmc_i(out2),
|
| 428 |
|
|
.o(out1)
|
| 429 |
|
|
);
|
| 430 |
|
|
|
| 431 |
|
|
// Sum the channels going to the filter
|
| 432 |
|
|
PSGChannelSummer u7
|
| 433 |
|
|
(
|
| 434 |
|
|
.clk_i(clk_i),
|
| 435 |
|
|
.cnt(cnt),
|
| 436 |
|
|
.outctrl(filt),
|
| 437 |
|
|
.tmc_i(out2),
|
| 438 |
|
|
.o(filtin1)
|
| 439 |
|
|
);
|
| 440 |
|
|
|
| 441 |
|
|
// The FIR filter
|
| 442 |
|
|
PSGFilter u8
|
| 443 |
|
|
(
|
| 444 |
|
|
.rst(rst_i),
|
| 445 |
|
|
.clk(clk_i),
|
| 446 |
|
|
.cnt(cnt),
|
| 447 |
|
|
.wr(we_i && stb_i && adr_i[6:4]==3'b101),
|
| 448 |
|
|
.adr(adr_i[3:0]),
|
| 449 |
|
|
.din({dat_i[15],dat_i[11:0]}),
|
| 450 |
|
|
.i(filtin1[21:7]),
|
| 451 |
|
|
.o(filt_o)
|
| 452 |
|
|
);
|
| 453 |
|
|
|
| 454 |
|
|
// Sum the filtered and unfiltered output
|
| 455 |
|
|
PSGOutputSummer u9
|
| 456 |
|
|
(
|
| 457 |
|
|
.clk_i(clk_i),
|
| 458 |
|
|
.cnt(cnt),
|
| 459 |
|
|
.ufi(out1),
|
| 460 |
|
|
.fi({filt_o,7'b0}),
|
| 461 |
|
|
.o(out3)
|
| 462 |
|
|
);
|
| 463 |
|
|
|
| 464 |
|
|
// Last stage:
|
| 465 |
|
|
// Adjust output according to master volume
|
| 466 |
|
|
PSGMasterVolumeControl u10
|
| 467 |
|
|
(
|
| 468 |
|
|
.rst_i(rst_i),
|
| 469 |
|
|
.clk_i(clk_i),
|
| 470 |
|
|
.i(out3[21:6]),
|
| 471 |
|
|
.volume(volume),
|
| 472 |
|
|
.o(out4)
|
| 473 |
|
|
);
|
| 474 |
|
|
|
| 475 |
|
|
assign o = out4[19:8];
|
| 476 |
|
|
|
| 477 |
|
|
endmodule
|
| 478 |
|
|
|
