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robfinch |
/* ============================================================================
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(C) 2007 Robert Finch
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All rights reserved.
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rob@birdcomputer.ca
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PSGChannelSummer.v
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Sums the channel outputs.
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This source code is available for evaluation and validation purposes
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only. This copyright statement and disclaimer must remain present in
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the file.
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NO WARRANTY.
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THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
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EXPRESS OR IMPLIED. The user must assume the entire risk of using the
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Work.
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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
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INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
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THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
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IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
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IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
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LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
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AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
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LOSSES RELATING TO SUCH UNAUTHORIZED USE.
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Spartan3
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1255 LUTs / 975 slices / 56MHz
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============================================================================ */
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module PSGChannelSummer(clk_i, cnt, outctrl, tmc_i, o);
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input clk_i; // master clock
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input [7:0] cnt; // select counter
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input [3:0] outctrl; // channel output enable control
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input [19:0] tmc_i; // time-multiplexed channel input
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output [21:0] o; // summed output
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reg [21:0] o;
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// channel select signal
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wire [1:0] sel = cnt[1:0];
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always @(posedge clk_i)
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if (cnt==8'd0)
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o <= 22'd0 + (tmc_i & {20{outctrl[sel]}});
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else if (cnt < 8'd4)
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o <= o + (tmc_i & {20{outctrl[sel]}});
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endmodule
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