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/* ============================================================================
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(C) 2007 Robert Finch
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All rights reserved.
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PSGEnvGen.v
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Version 1.1
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ADSR envelope generator.
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This source code is available for evaluation and validation purposes
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only. This copyright statement and disclaimer must remain present in
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the file.
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NO WARRANTY.
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THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
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EXPRESS OR IMPLIED. The user must assume the entire risk of using the
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Work.
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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
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INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
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THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
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IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
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IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
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LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
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AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
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LOSSES RELATING TO SUCH UNAUTHORIZED USE.
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Note that this envelope generator directly uses the values for attack,
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decay, sustain, and release. The original SID had to use four bit codes
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and lookup tables due to register limitations. This generator is
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built assuming there aren't any such register limitations.
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A wrapper could be built to provide that functionality.
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This component isn't really meant to be used in isolation. It is
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intended to be integrated into a larger audio component (eg SID
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emulator). The host component should take care of wrapping the control
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signals into a register array.
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The 'cnt' signal acts a prescaler used to determine the base frequency
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used to generate envelopes. The core expects to be driven at
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approximately a 1.0MHz rate for proper envelope generation. This is
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accomplished using the 'cnt' signal, which should the output of a
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counter used to divide the master clock frequency down to approximately
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a 1MHz rate. Therefore, the master clock frequency must be at least 4MHz
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for a 4 channel generator, 8MHZ for an 8 channel generator. The test
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system uses a 66.667MHz master clock and 'cnt' is the output of a seven
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bit counter that divides by 66.
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Note the resource space optimization. Rather than simply build a single
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channel ADSR envelope generator and instantiate it four or eight times,
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This unit uses a single envelope generator and time-multiplexes the
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controls from four (or eight) different channels. The ADSR is just
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complex enough that it's less expensive resource wise to multiplex the
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control signals. The luxury of time division multiplexing can be used
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here since audio signals are low frequency. The time division multiplex
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means that we need a clock that's four (or eight) times faster than
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would be needed if independent ADSR's were used. This probably isn't a
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problem for most cases.
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Spartan3
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Webpack 9.1i xc3s1000-4ft256
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522 LUTs / 271 slices / 81.155 MHz (speed)
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============================================================================ */
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/*
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sample attack values / rates
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----------------------------
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8 2ms
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32 8ms
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64 16ms
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96 24ms
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152 38ms
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224 56ms
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272 68ms
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320 80ms
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400 100ms
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955 239ms
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1998 500ms
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3196 800ms
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3995 1s
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12784 3.2s
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21174 5.3s
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31960 8s
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rate = 990.00ns x 256 x value
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*/
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// envelope generator states
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`define ENV_IDLE 0
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`define ENV_ATTACK 1
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`define ENV_DECAY 2
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`define ENV_SUSTAIN 3
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`define ENV_RELEASE 4
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//`define CHANNELS8
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// Envelope generator
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module PSGEnvGen(rst, clk, cnt,
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gate,
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attack0, attack1, attack2, attack3,
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decay0, decay1, decay2, decay3,
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sustain0, sustain1, sustain2, sustain3,
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relese0, relese1, relese2, relese3,
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`ifdef CHANNELS8
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attack4, attack5, attack6, attack7,
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decay4, decay5, decay6, decay7,
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sustain4, sustain5, sustain6, sustain7,
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relese4, relese5, relese6, relese7,
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`endif
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o);
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parameter pChannels = 4;
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parameter pPrescalerBits = 5;
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input rst; // reset
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input clk; // core clock
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input [pPrescalerBits-1:0] cnt; // clock rate prescaler
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input [3:0] attack0;
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input [3:0] attack1;
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input [3:0] attack2;
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input [3:0] attack3;
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input [3:0] decay0;
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input [3:0] decay1;
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input [3:0] decay2;
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input [3:0] decay3;
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input [3:0] sustain0;
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input [3:0] sustain1;
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input [3:0] sustain2;
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input [3:0] sustain3;
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input [3:0] relese0;
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input [3:0] relese1;
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input [3:0] relese2;
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input [3:0] relese3;
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`ifdef CHANNELS8
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input [7:0] gate;
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input [3:0] attack4;
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input [3:0] attack5;
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input [3:0] attack6;
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input [3:0] attack7;
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input [3:0] decay4;
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input [3:0] decay5;
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input [3:0] decay6;
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input [3:0] decay7;
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input [3:0] sustain4;
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input [3:0] sustain5;
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input [3:0] sustain6;
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input [3:0] sustain7;
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input [3:0] relese4;
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input [3:0] relese5;
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input [3:0] relese6;
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input [3:0] relese7;
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`else
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input [3:0] gate;
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`endif
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output [7:0] o;
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reg [7:0] sustain;
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reg [15:0] attack;
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reg [17:0] decay;
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reg [17:0] relese;
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`ifdef CHANNELS8
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reg [7:0] envCtr [7:0];
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reg [7:0] envCtr2 [7:0]; // for counting intervals
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reg [7:0] iv[7:0]; // interval value for decay/release
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reg [2:0] icnt[7:0]; // interval count
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reg [19:0] envDvn [7:0];
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reg [2:0] envState [7:0];
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`else
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reg [7:0] envCtr [3:0];
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reg [7:0] envCtr2 [3:0];
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reg [7:0] iv[3:0]; // interval value for decay/release
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reg [2:0] icnt[3:0]; // interval count
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reg [19:0] envDvn [3:0];
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reg [2:0] envState [3:0];
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`endif
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reg [2:0] envStateNxt;
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reg [15:0] envStepPeriod; // determines the length of one step of the envelope generator
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reg [7:0] envCtrx;
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reg [19:0] envDvnx;
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wire [3:0] attack_x;
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wire [3:0] decay_x;
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wire [3:0] sustain_x;
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wire [3:0] relese_x;
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integer n;
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// Decodes a 4-bit code into an attack value
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function [15:0] AttackDecode;
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input [3:0] atk;
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begin
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case(atk)
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4'd0: AttackDecode = 16'd8;
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4'd1: AttackDecode = 16'd32;
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4'd2: AttackDecode = 16'd63;
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4'd3: AttackDecode = 16'd95;
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4'd4: AttackDecode = 16'd150;
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4'd5: AttackDecode = 16'd221;
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4'd6: AttackDecode = 16'd268;
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4'd7: AttackDecode = 16'd316;
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4'd8: AttackDecode = 16'd395;
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4'd9: AttackDecode = 16'd986;
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4'd10: AttackDecode = 16'd1973;
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4'd11: AttackDecode = 16'd3157;
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4'd12: AttackDecode = 16'd3946;
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4'd13: AttackDecode = 16'd11837;
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4'd14: AttackDecode = 16'd19729;
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4'd15: AttackDecode = 16'd31566;
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endcase
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end
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endfunction
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// Decodes a 4-bit code into a decay/release value
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function [15:0] DecayDecode;
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input [3:0] dec;
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begin
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case(dec)
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4'd0: DecayDecode = 17'd24;
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4'd1: DecayDecode = 17'd95;
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4'd2: DecayDecode = 17'd190;
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4'd3: DecayDecode = 17'd285;
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4'd4: DecayDecode = 17'd452;
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4'd5: DecayDecode = 17'd665;
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4'd6: DecayDecode = 17'd808;
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4'd7: DecayDecode = 17'd951;
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4'd8: DecayDecode = 17'd1188;
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4'd9: DecayDecode = 17'd2971;
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4'd10: DecayDecode = 17'd5942;
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4'd11: DecayDecode = 17'd9507;
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4'd12: DecayDecode = 17'd11884;
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4'd13: DecayDecode = 17'd35651;
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4'd14: DecayDecode = 17'd59418;
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4'd15: DecayDecode = 17'd95068;
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endcase
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end
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endfunction
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`ifdef CHANNELS8
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wire [2:0] sel = cnt[2:0];
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always @(sel or
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attack0 or attack1 or attack2 or attack3 or
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attack4 or attack5 or attack6 or attack7)
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case (sel)
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0: attack_x <= attack0;
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1: attack_x <= attack1;
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2: attack_x <= attack2;
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3: attack_x <= attack3;
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4: attack_x <= attack4;
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5: attack_x <= attack5;
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6: attack_x <= attack6;
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7: attack_x <= attack7;
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endcase
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always @(sel or
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decay0 or decay1 or decay2 or decay3 or
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decay4 or decay5 or decay6 or decay7)
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case (sel)
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0: decay_x <= decay0;
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1: decay_x <= decay1;
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2: decay_x <= decay2;
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3: decay_x <= decay3;
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4: decay_x <= decay4;
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5: decay_x <= decay5;
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6: decay_x <= decay6;
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7: decay_x <= decay7;
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endcase
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always @(sel or
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sustain0 or sustain1 or sustain2 or sustain3 or
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sustain4 or sustain5 or sustain6 or sustain7)
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case (sel)
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0: sustain <= sustain0;
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1: sustain <= sustain1;
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2: sustain <= sustain2;
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3: sustain <= sustain3;
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4: sustain <= sustain4;
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5: sustain <= sustain5;
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6: sustain <= sustain6;
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7: sustain <= sustain7;
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endcase
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always @(sel or
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relese0 or relese1 or relese2 or relese3 or
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relese4 or relese5 or relese6 or relese7)
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case (sel)
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0: relese <= relese0;
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1: relese <= relese1;
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2: relese <= relese2;
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3: relese <= relese3;
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4: relese <= relese4;
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5: relese <= relese5;
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6: relese <= relese6;
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7: relese <= relese7;
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endcase
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`else
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wire [1:0] sel = cnt[1:0];
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mux4to1 #(4) u1 (
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.e(1'b1),
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.s(sel),
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.i0(attack0),
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.i1(attack1),
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.i2(attack2),
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.i3(attack3),
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.z(attack_x)
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);
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mux4to1 #(12) u2 (
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.e(1'b1),
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.s(sel),
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.i0(decay0),
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.i1(decay1),
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.i2(decay2),
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.i3(decay3),
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.z(decay_x)
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);
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mux4to1 #(8) u3 (
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.e(1'b1),
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.s(sel),
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.i0(sustain0),
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.i1(sustain1),
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.i2(sustain2),
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.i3(sustain3),
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.z(sustain_x)
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);
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mux4to1 #(12) u4 (
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.e(1'b1),
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.s(sel),
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.i0(relese0),
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.i1(relese1),
|
| 343 |
|
|
.i2(relese2),
|
| 344 |
|
|
.i3(relese3),
|
| 345 |
|
|
.z(relese_x)
|
| 346 |
|
|
);
|
| 347 |
|
|
|
| 348 |
|
|
`endif
|
| 349 |
|
|
|
| 350 |
|
|
always @(attack_x)
|
| 351 |
|
|
attack <= AttackDecode(attack_x);
|
| 352 |
|
|
|
| 353 |
|
|
always @(decay_x)
|
| 354 |
|
|
decay <= DecayDecode(decay_x);
|
| 355 |
|
|
|
| 356 |
|
|
always @(sustain_x)
|
| 357 |
|
|
sustain <= {sustain_x,sustain_x};
|
| 358 |
|
|
|
| 359 |
|
|
always @(relese_x)
|
| 360 |
|
|
relese <= DecayDecode(relese_x);
|
| 361 |
|
|
|
| 362 |
|
|
|
| 363 |
|
|
always @(sel)
|
| 364 |
|
|
envCtrx <= envCtr[sel];
|
| 365 |
|
|
|
| 366 |
|
|
always @(sel)
|
| 367 |
|
|
envDvnx <= envDvn[sel];
|
| 368 |
|
|
|
| 369 |
|
|
|
| 370 |
|
|
// Envelope generate state machine
|
| 371 |
|
|
// Determine the next envelope state
|
| 372 |
|
|
always @(sel or gate or sustain)
|
| 373 |
|
|
begin
|
| 374 |
|
|
case (envState[sel])
|
| 375 |
|
|
`ENV_IDLE:
|
| 376 |
|
|
if (gate[sel])
|
| 377 |
|
|
envStateNxt <= `ENV_ATTACK;
|
| 378 |
|
|
else
|
| 379 |
|
|
envStateNxt <= `ENV_IDLE;
|
| 380 |
|
|
`ENV_ATTACK:
|
| 381 |
|
|
if (envCtrx==8'hFE) begin
|
| 382 |
|
|
if (sustain==8'hFF)
|
| 383 |
|
|
envStateNxt <= `ENV_SUSTAIN;
|
| 384 |
|
|
else
|
| 385 |
|
|
envStateNxt <= `ENV_DECAY;
|
| 386 |
|
|
end
|
| 387 |
|
|
else
|
| 388 |
|
|
envStateNxt <= `ENV_ATTACK;
|
| 389 |
|
|
`ENV_DECAY:
|
| 390 |
|
|
if (envCtrx==sustain)
|
| 391 |
|
|
envStateNxt <= `ENV_SUSTAIN;
|
| 392 |
|
|
else
|
| 393 |
|
|
envStateNxt <= `ENV_DECAY;
|
| 394 |
|
|
`ENV_SUSTAIN:
|
| 395 |
|
|
if (~gate[sel])
|
| 396 |
|
|
envStateNxt <= `ENV_RELEASE;
|
| 397 |
|
|
else
|
| 398 |
|
|
envStateNxt <= `ENV_SUSTAIN;
|
| 399 |
|
|
`ENV_RELEASE: begin
|
| 400 |
|
|
if (envCtrx==8'h00)
|
| 401 |
|
|
envStateNxt <= `ENV_IDLE;
|
| 402 |
|
|
else if (gate[sel])
|
| 403 |
|
|
envStateNxt <= `ENV_SUSTAIN;
|
| 404 |
|
|
else
|
| 405 |
|
|
envStateNxt <= `ENV_RELEASE;
|
| 406 |
|
|
end
|
| 407 |
|
|
// In case of hardware problem
|
| 408 |
|
|
default:
|
| 409 |
|
|
envStateNxt <= `ENV_IDLE;
|
| 410 |
|
|
endcase
|
| 411 |
|
|
end
|
| 412 |
|
|
|
| 413 |
|
|
always @(posedge clk)
|
| 414 |
|
|
if (rst) begin
|
| 415 |
|
|
for (n = 0; n < pChannels; n = n + 1)
|
| 416 |
|
|
envState[n] <= `ENV_IDLE;
|
| 417 |
|
|
end
|
| 418 |
|
|
else if (cnt < pChannels)
|
| 419 |
|
|
envState[sel] <= envStateNxt;
|
| 420 |
|
|
|
| 421 |
|
|
|
| 422 |
|
|
// Handle envelope counter
|
| 423 |
|
|
always @(posedge clk)
|
| 424 |
|
|
if (rst) begin
|
| 425 |
|
|
for (n = 0; n < pChannels; n = n + 1) begin
|
| 426 |
|
|
envCtr[n] <= 0;
|
| 427 |
|
|
envCtr2[n] <= 0;
|
| 428 |
|
|
icnt[n] <= 0;
|
| 429 |
|
|
iv[n] <= 0;
|
| 430 |
|
|
end
|
| 431 |
|
|
end
|
| 432 |
|
|
else if (cnt < pChannels) begin
|
| 433 |
|
|
case (envState[sel])
|
| 434 |
|
|
`ENV_IDLE:
|
| 435 |
|
|
begin
|
| 436 |
|
|
envCtr[sel] <= 0;
|
| 437 |
|
|
envCtr2[sel] <= 0;
|
| 438 |
|
|
icnt[sel] <= 0;
|
| 439 |
|
|
iv[sel] <= 0;
|
| 440 |
|
|
end
|
| 441 |
|
|
`ENV_SUSTAIN:
|
| 442 |
|
|
begin
|
| 443 |
|
|
envCtr2[sel] <= 0;
|
| 444 |
|
|
icnt[sel] <= 0;
|
| 445 |
|
|
iv[sel] <= sustain >> 3;
|
| 446 |
|
|
end
|
| 447 |
|
|
`ENV_ATTACK:
|
| 448 |
|
|
begin
|
| 449 |
|
|
icnt[sel] <= 0;
|
| 450 |
|
|
iv[sel] <= (8'hff - sustain) >> 3;
|
| 451 |
|
|
if (envDvnx==20'h0) begin
|
| 452 |
|
|
envCtr2[sel] <= 0;
|
| 453 |
|
|
envCtr[sel] <= envCtrx + 1;
|
| 454 |
|
|
end
|
| 455 |
|
|
end
|
| 456 |
|
|
`ENV_DECAY,
|
| 457 |
|
|
`ENV_RELEASE:
|
| 458 |
|
|
if (envDvnx==20'h0) begin
|
| 459 |
|
|
envCtr[sel] <= envCtrx - 1;
|
| 460 |
|
|
if (envCtr2[sel]==iv[sel]) begin
|
| 461 |
|
|
envCtr2[sel] <= 0;
|
| 462 |
|
|
if (icnt[sel] < 3'd7)
|
| 463 |
|
|
icnt[sel] <= icnt[sel] + 1;
|
| 464 |
|
|
end
|
| 465 |
|
|
else
|
| 466 |
|
|
envCtr2[sel] <= envCtr2[sel] + 1;
|
| 467 |
|
|
end
|
| 468 |
|
|
endcase
|
| 469 |
|
|
end
|
| 470 |
|
|
|
| 471 |
|
|
// Determine envelope divider adjustment source
|
| 472 |
|
|
always @(sel or attack or decay or relese)
|
| 473 |
|
|
begin
|
| 474 |
|
|
case(envState[sel])
|
| 475 |
|
|
`ENV_ATTACK: envStepPeriod <= attack;
|
| 476 |
|
|
`ENV_DECAY: envStepPeriod <= decay;
|
| 477 |
|
|
`ENV_RELEASE: envStepPeriod <= relese;
|
| 478 |
|
|
default: envStepPeriod <= 16'h0;
|
| 479 |
|
|
endcase
|
| 480 |
|
|
end
|
| 481 |
|
|
|
| 482 |
|
|
|
| 483 |
|
|
// double the delay at appropriate points
|
| 484 |
|
|
// for exponential modelling
|
| 485 |
|
|
wire [19:0] envStepPeriod1 = {4'b0,envStepPeriod} << icnt[sel];
|
| 486 |
|
|
|
| 487 |
|
|
|
| 488 |
|
|
// handle the clock divider
|
| 489 |
|
|
// loadable down counter
|
| 490 |
|
|
// This sets the period of each step of the envelope
|
| 491 |
|
|
always @(posedge clk)
|
| 492 |
|
|
if (rst) begin
|
| 493 |
|
|
for (n = 0; n < pChannels; n = n + 1)
|
| 494 |
|
|
envDvn[n] <= 0;
|
| 495 |
|
|
end
|
| 496 |
|
|
else if (cnt < pChannels) begin
|
| 497 |
|
|
if (envDvnx==20'h0)
|
| 498 |
|
|
envDvn[sel] <= envStepPeriod1;
|
| 499 |
|
|
else
|
| 500 |
|
|
envDvn[sel] <= envDvnx - 1;
|
| 501 |
|
|
end
|
| 502 |
|
|
|
| 503 |
|
|
assign o = envCtrx;
|
| 504 |
|
|
|
| 505 |
|
|
endmodule
|
| 506 |
|
|
|
| 507 |
|
|
|
