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[/] [rtf68ksys/] [trunk/] [rtl/] [verilog/] [PSGNoteOutMux.v] - Blame information for rev 2

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1 2 robfinch
/* ============================================================================
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        (C) 2007  Robert Finch
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        All rights reserved.
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        bcPSGNoteOutMux.v
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        Version 1.0
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    This source code is available for evaluation and validation purposes
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    only. This copyright statement and disclaimer must remain present in
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    the file.
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        NO WARRANTY.
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    THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
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    EXPRESS OR IMPLIED. The user must assume the entire risk of using the
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    Work.
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    IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
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    INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
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    THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
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    IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
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    IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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    REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
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    LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
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    AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
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    LOSSES RELATING TO SUCH UNAUTHORIZED USE.
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        Selects from one of five waveforms for output. Selected waveform
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        outputs are anded together. This is approximately how the
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        original SID worked.
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        Spartan3
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        Webpack 9.1i xc3s1000-4ft256
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        36 LUTs / 21 slices / 11ns
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============================================================================ */
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module PSGNoteOutMux(s, a, b, c, d, e, o);
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parameter WID = 12;
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input [4:0] s;
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input [WID-1:0] a,b,c,d,e;
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output [WID-1:0] o;
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wire [WID-1:0] o1,o2,o3,o4,o5;
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assign o1 = s[4] ? e : {WID{1'b1}};
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assign o2 = s[3] ? d : {WID{1'b1}};
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assign o3 = s[2] ? c : {WID{1'b1}};
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assign o4 = s[1] ? b : {WID{1'b1}};
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assign o5 = s[0] ? a : {WID{1'b1}};
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assign o = o1 & o2 & o3 & o4 & o5;
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endmodule
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