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[/] [rtf68ksys/] [trunk/] [rtl/] [verilog/] [ParallelToSerial.v] - Blame information for rev 2

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1 2 robfinch
// ============================================================================
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//      2006,2007,2011  Robert Finch
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//      robfinch@<remove>sympatico.ca
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//
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//      ParallelToSerial.v
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//              Parallel to serial data converter (shift register).
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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//
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module ParallelToSerial(rst, clk, ce, ld, qin, d, qh);
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parameter WID=8;
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input rst;                      // reset
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input clk;                      // clock
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input ce;                       // clock enable
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input ld;                       // load
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input qin;                      // serial shifting input
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input [WID:1] d;        // data to load
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output qh;                      // serial output
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reg [WID:1] q;
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always @(posedge clk)
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        if (rst)
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                q <= 0;
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        else if (ce) begin
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                if (ld)
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                        q <= d;
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                else
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                        q <= {q[WID-1:1],qin};
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        end
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assign qh = q[WID];
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endmodule

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