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[/] [rtf68ksys/] [trunk/] [rtl/] [verilog/] [WXGASyncGen1680x1050_60Hz_tb.v] - Blame information for rev 2

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1 2 robfinch
// ============================================================================
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// 2011 Robert Finch
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//
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//      WXGASyncGen1680x1050_60Hz_tb.v
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//              WXGA sync generator test bench
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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module WXGASyncGen1680x1050_60Hz_tb();
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reg clk;
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reg rst;
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initial begin
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        clk = 1;
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        rst = 0;
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        #100 rst = 1;
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        #100 rst = 0;
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end
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always #6.8000 clk = ~clk;      //  73.529 MHz
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WXGASyncGen1680x1050_60Hz u1
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(
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.rst(rst),
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.clk(clk),
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.hSync(),
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.vSync(),
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.blank(),
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.border(),
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.eol(),
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.eof()
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);
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endmodule

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