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[/] [rtf68ksys/] [trunk/] [rtl/] [verilog/] [dac121s101.v] - Blame information for rev 2

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//=============================================================================
//  dac121s101
//  - DAC (digital to analogue) converter interface core
//
//
//      2010 Robert T Finch
//      robfinch<remove>@FPGAfield.ca
//
//
//      This source code is available only for veiwing, testing and evaluation
//      purposes. Any commercial use requires a license. This copyright
//      statement and disclaimer must remain present in the file.
//
//
//      NO WARRANTY.
//  THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
//      EXPRESS OR IMPLIED. The user must assume the entire risk of using the
//      Work.
//
//      IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
//  INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
//  THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
//      IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
//      IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
//      REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
//      LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
//      AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
//      LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//
//  Webpack 9.2i xc3s1200e 4fg320
//  38 slices / 71 LUTs / 183.824 MHz
//  36 ff's
//
//=============================================================================
 
module dac121s101(rst_i, clk_i, cyc_i, stb_i, ack_o, we_i, dat_i, sclk, sync, d);
parameter pClkFreq=60000000;
parameter pPrescale=pClkFreq/50000000 + 1;      //2x freq
// states
parameter IDLE=4'd0;
parameter LOAD=4'd1;
parameter SHIFT=4'd2;
parameter TERM=4'd3;
 
// SYSCON
input rst_i;
input clk_i;
 
input cyc_i;
input stb_i;
input we_i;
output ack_o;
input [15:0] dat_i;
 
output sclk;
output sync;
output d;
 
// Registered outputs
reg sclk;
reg sync;
 
reg [1:0] state;
reg pe_sclk;
reg [7:0] ps_cnt;        // prescale counter
reg [3:0] cnt;           // shift bit counter
reg [15:0] dd;
reg ack;
 
assign ack_o = cyc_i & stb_i & ack;
 
 
// Prescale the system clock
// The DAC has a max clock frequency of 30MHz.
//
always @(posedge clk_i)
if (rst_i) begin
        ps_cnt <= 8'd1;
        sclk <= 1'b0;
        pe_sclk <= 1'b0;
end
else begin
        pe_sclk <= 1'b0;
        if (ps_cnt==pPrescale) begin
                ps_cnt <= 8'd1;
                sclk <= !sclk;
                pe_sclk <= sclk==1'b0;
        end
        else
                ps_cnt <= ps_cnt + 8'd1;
end
 
 
always @(posedge clk_i)
if (rst_i) begin
        ack <= 1'b0;
        sync <= 1'b1;
        dd <= 16'h0000;
        cnt <= 4'd0;
        state <= IDLE;
end
else begin
 
        if (!cyc_i || !stb_i)
                ack <= 1'b0;
 
        case(state)
        IDLE:
                if (cyc_i & stb_i & we_i) begin
                        state <= LOAD;
                        dd[11:0] <= dat_i[13:0];
                        dd[15:12] <= 4'b0000;
                        ack <= 1'b1;
                end
        LOAD:
                if (pe_sclk) begin
                        sync <= 1'b0;
                        cnt <= 4'd0;
                        state <= SHIFT;
                end
        SHIFT:
                if (pe_sclk) begin
                        dd <= {dd[14:0],1'b0};
                        cnt <= cnt + 4'd1;
                        if (cnt==4'd15)
                                state <= TERM;
                end
        TERM:
                if (pe_sclk) begin
                        sync <= 1'b1;
                        state <= IDLE;
                end
        default:
                state <= IDLE;
        endcase
end
 
assign d = dd[15];
 
endmodule

Line No.	Rev	Author	Line
1	2	robfinch	`//=============================================================================`
2			`// dac121s101`
3			`// - DAC (digital to analogue) converter interface core`
4			`//`
5			`//`
6			`// 2010 Robert T Finch`
7			`// robfinch<remove>@FPGAfield.ca`
8			`//`
9			`//`
10			`// This source code is available only for veiwing, testing and evaluation`
11			`// purposes. Any commercial use requires a license. This copyright`
12			`// statement and disclaimer must remain present in the file.`
13			`//`
14			`//`
15			`// NO WARRANTY.`
16			`// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER`
17			`// EXPRESS OR IMPLIED. The user must assume the entire risk of using the`
18			`// Work.`
19			`//`
20			`// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY`
21			`// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO`
22			`// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.`
23			`//`
24			`// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK`
25			`// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN`
26			`// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN`
27			`// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU`
28			`// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR`
29			`// LOSSES RELATING TO SUCH UNAUTHORIZED USE.`
30			`//`
31			`//`
32			`// Webpack 9.2i xc3s1200e 4fg320`
33			`// 38 slices / 71 LUTs / 183.824 MHz`
34			`// 36 ff's`
35			`//`
36			`//=============================================================================`
37
38			`module dac121s101(rst_i, clk_i, cyc_i, stb_i, ack_o, we_i, dat_i, sclk, sync, d);`
39			`parameter pClkFreq=60000000;`
40			`parameter pPrescale=pClkFreq/50000000 + 1; //2x freq`
41			`// states`
42			`parameter IDLE=4'd0;`
43			`parameter LOAD=4'd1;`
44			`parameter SHIFT=4'd2;`
45			`parameter TERM=4'd3;`
46
47			`// SYSCON`
48			`input rst_i;`
49			`input clk_i;`
50
51			`input cyc_i;`
52			`input stb_i;`
53			`input we_i;`
54			`output ack_o;`
55			`input [15:0] dat_i;`
56
57			`output sclk;`
58			`output sync;`
59			`output d;`
60
61			`// Registered outputs`
62			`reg sclk;`
63			`reg sync;`
64
65			`reg [1:0] state;`
66			`reg pe_sclk;`
67			`reg [7:0] ps_cnt; // prescale counter`
68			`reg [3:0] cnt; // shift bit counter`
69			`reg [15:0] dd;`
70			`reg ack;`
71
72			`assign ack_o = cyc_i & stb_i & ack;`
73
74
75			`// Prescale the system clock`
76			`// The DAC has a max clock frequency of 30MHz.`
77			`//`
78			`always @(posedge clk_i)`
79			`if (rst_i) begin`
80			`ps_cnt <= 8'd1;`
81			`sclk <= 1'b0;`
82			`pe_sclk <= 1'b0;`
83			`end`
84			`else begin`
85			`pe_sclk <= 1'b0;`
86			`if (ps_cnt==pPrescale) begin`
87			`ps_cnt <= 8'd1;`
88			`sclk <= !sclk;`
89			`pe_sclk <= sclk==1'b0;`
90			`end`
91			`else`
92			`ps_cnt <= ps_cnt + 8'd1;`
93			`end`
94
95
96			`always @(posedge clk_i)`
97			`if (rst_i) begin`
98			`ack <= 1'b0;`
99			`sync <= 1'b1;`
100			`dd <= 16'h0000;`
101			`cnt <= 4'd0;`
102			`state <= IDLE;`
103			`end`
104			`else begin`
105
106			`if (!cyc_i \|\| !stb_i)`
107			`ack <= 1'b0;`
108
109			`case(state)`
110			`IDLE:`
111			`if (cyc_i & stb_i & we_i) begin`
112			`state <= LOAD;`
113			`dd[11:0] <= dat_i[13:0];`
114			`dd[15:12] <= 4'b0000;`
115			`ack <= 1'b1;`
116			`end`
117			`LOAD:`
118			`if (pe_sclk) begin`
119			`sync <= 1'b0;`
120			`cnt <= 4'd0;`
121			`state <= SHIFT;`
122			`end`
123			`SHIFT:`
124			`if (pe_sclk) begin`
125			`dd <= {dd[14:0],1'b0};`
126			`cnt <= cnt + 4'd1;`
127			`if (cnt==4'd15)`
128			`state <= TERM;`
129			`end`
130			`TERM:`
131			`if (pe_sclk) begin`
132			`sync <= 1'b1;`
133			`state <= IDLE;`
134			`end`
135			`default:`
136			`state <= IDLE;`
137			`endcase`
138			`end`
139
140			`assign d = dd[15];`
141
142			`endmodule`

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[/] [rtf68ksys/] [trunk/] [rtl/] [verilog/] [dac121s101.v] - Blame information for rev 2