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[/] [rtf68ksys/] [trunk/] [rtl/] [verilog/] [mux4to1.v] - Blame information for rev 6

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1 2 robfinch 
// (C) 2007  Robert T Finch
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// All Rights Reserved.
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//
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// Verilog 1995
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//
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// Webpack 9.1i  xc3s1000-4ft256
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//  slices /  LUTs / MHz
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module mux4to1(e, s, i0, i1, i2, i3, z);
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        parameter WID=4;
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        input e;
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        input [1:0] s;
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        input [WID:1] i0;
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        input [WID:1] i1;
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        input [WID:1] i2;
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        input [WID:1] i3;
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        output [WID:1] z;
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        reg [WID:1] z;
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        always @(e or s or i0 or i1 or i2 or i3)
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                if (!e)
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                        z <= {WID{1'b0}};
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                else begin
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                        case(s)
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                        2'b00:  z <= i0;
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                        2'b01:  z <= i1;
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                        2'b10:  z <= i2;
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                        2'b11:  z <= i3;
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                        endcase
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                end
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endmodule

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